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An overview of FPGA based deep learning accelerators: Challenges and opportunities 21

An overview of FPGA based deep learning accelerators: Challe...

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21st IEEE international Conference on high performance computing and Communications, 17th IEEE international Conference on Smart City and 5th IEEE international Conference on Data Science and Systems, HPCC/SmartCity/DSS 2019

作者： Wang, Teng Wang, Chao Zhou, Xuehai Chen, Huaping University of Science and Technology of China School of Software Engineering Suzhou China University of Science and Technology of China School of Computer Science and Technology Suzhou China

ISBN: (纸本)9781728120584

With the rapid development of in-depth learning, neural network and deep learning algorithms have been widely used in various fields, e.g., image, video and voice processing. However, the neural network model is getting larger and larger, which is expressed in the calculation of model parameters. Although a wealth of existing efforts on GPU platforms currently used by researchers for improving computing performance, dedicated hardware solutions are essential and emerging to provide advantages over pure software solutions. In this paper, we systematically investigate the neural network accelerator based on Field-Programmable Gate Array(FPGA). Specifically, we respectively review the accelerators designed for specific problems, specific algorithms, algorithm features, and general templates. We also compared the design and implementation of the accelerator based on FPGA under different devices and network models and compared it with the versions of CPU and GPU. Finally, we present to discuss the advantages and disadvantages of accelerators on FPGA platforms and to further explore the opportunities for future research. © 2019 IEEE.

关键词： Deep learning

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Dynamic scheduling of EDA scientific workflows in hybrid computing environments 21

Dynamic scheduling of EDA scientific workflows in hybrid com...

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作者： Shen, Qinghao Yu, Ce Xiao, Jian Tang, Shanjiang Meng, Xiangfei Li, Jianzeng School of Computer Science and Technology College of Intelligence and Computing Tianjin University Tianjin300350 China National Supercomputer Center in Tianjin Tianjin300457 China

ISBN: (纸本)9781728120584

With the increasing scale and complexity of Very-Large-Scale Integration (VLSI), Electronic Design Automation (EDA) technology is undergoing rapid development, and it's tools are becoming ever more diverse. The EDA scientific workflow refers to the combination of tasks at each stage in EDA design, e.g., RTL simulation, logic synthesis, layout (placement and routing), and timing simulation, etc. The execution of these tasks is quite inflexible and consumes a lot of time and resources, because EDA design is computing intensive. Due to the diversity of computing resource requirements, single computing environment cannot support the execution of EDA scientific workflows, so hybrid computing environments (HCE) are indispensable for the integration of multiple EDA tools. Besides, the licenses of EDA tools are limited and expensive, which limit the available resources required for EDA tasks. However, the existing dynamic algorithms are not suitable for task characteristics and computing environments of EDA scientific workflows. To solve these problems, we propose an efficient algorithm to schedule EDA scientific workflows dynamically based on HCE, including Cloud and high performance computing (HPC) clusters, which takes into account characteristics of each task and constraints of licenses for using EDA commercial tools. In this paper, first, multiple Directed Acyclic Graphs (DAGs) are adopted for representing the EDA scientific workflows and task dependencies. Then, a dynamic scheduling algorithm is used to implement task selection and resource allocation. Moreover, we achieve a tradeoff between efficiency and user fairness. Finally, the proposed algorithm is evaluated in simulated experiments. Experimental results show that it can reduce overall makespan by up to 26.9% and improve user fairness at least 23.04% than other algorithms. © 2019 IEEE.

关键词： Scheduling algorithms

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An anonymous conditional privacy-preserving authentication scheme for VANETs 21

An anonymous conditional privacy-preserving authentication s...

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作者： Li, Xincheng Liu, Yali Yin, Xinchun College of Information Engineering Yangzhou University Yangzhou China College of Computer Science and Technology Jiangsu Normal University Xuzhou China

ISBN: (纸本)9781728120584

Vehicular ad hoc networks (VANETs) have been growing rapidly because it can improve traffic safety and efficiency in transportation. In VANETs, messages are broadcast in wireless environment, which is vulnerable to be attacked in many ways. Accordingly, it is essential to authenticate the legitimation of vehicles to guarantee the performance of services. In this paper, we propose an anonymous conditional privacy-preserving authentication scheme based on message authentication code (MAC) for VANETs. With verifiable secret sharing (VSS), vehicles can obtain a group key for message generation and authentication after a mutual authentication phase. Security analysis and performance evaluation show that the proposed scheme satisfies basic security and privacy-preserving requirements and has a better performance compared with some existing schemes in terms of computational cost and communication overhead. © 2019 IEEE.

关键词： Authentication

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MG-buffer: A Read/write-optimized multi-grained buffer management scheme for database systems 21

MG-buffer: A Read/write-optimized multi-grained buffer manag...

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作者： Wang, Xiaoliang Jin, Peiquan Liu, Ruicheng Zhang, Zhou Wan, Shouhong Hua, Bei School of Computer Science and Technology University of Science and Technology of China Hefei230026 China Key Lab. of Electromagnetic Space Information Chinese Academy of Sciences Hefei230026 China

ISBN: (纸本)9781728120584

It is a common design in traditional DBMSs to use a page buffer consisting of fixed-sized pages to cache hot data. However, DBMSs have to read and cache at least one page even if one tuple is needed. As a result, there will be a number of unnecessary tuples resisting in the buffer, which will lower the efficiency of the buffer. This is even worse when the page size increases. Aiming to solve this problem, this work proposes to use a multi-grained buffer composed of a page buffer and a tuple buffer to improve the buffer efficiency. The page buffer is the same as usual, and the tuple buffer is to cache the hot or dirty tuples exactly requested by users. Following this idea, we present a new buffering scheme called MG-Buffer, which includes a so-called F-Buffer for pages and an S-Buffer for caching tuples migrated from F-Buffer. After introducing the architecture of MG-Buffer, we present the details of the operations for MG-Buffer, including migration and merging, read and write, and replacement. MG-Buffer is read-optimized because it can increase the hit ratio of the entire buffer. It is also write-optimized, because it first groups the dirty tuples cached in the S-Buffer before writing them to disks. We conduct trace-driven experiments on both magnetic disks and SSDs to evaluate MG-Buffer. The results suggest the efficiency of our proposal. Especially, MG-Buffer averagely achieves 20% higher hit ratio and reduces 20% more I/Os compared with traditional disk-based buffering schemes including LRU, 2Q, and LIRS. It also reduces 30% writes to SSD on average compared with existing SSD-aware buffering schemes like CFLRU, CFDC, and FD-Buffer. © 2019 IEEE.

关键词： Efficiency

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Efficient parallel sort on AVX-512-based multi-core and many-core architectures 21

Efficient parallel sort on AVX-512-based multi-core and many...

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作者： Yin, Zekun Zhang, Tianyu Muller, Andre Liu, Hui Wei, Yanjie Schmidt, Bertil Liu, Weiguo School of Software Shandong University Jinan China Shenzhen Research Institute Shandong University China Institute for Computer Science Johannes Gutenberg University Mainz Germany Shenzhen Institutes of Advanced Technology Chinese Academy of Sciences Shenzhen China National Supercomputing Center in Wuxi Wuxi China

ISBN: (纸本)9781728120584

Sorting kernels are a fundamental part of numerous applications. The performance of sorting implementations is usually limited by a variety of factors such as computing power, memory bandwidth, and branch mispredictions. In this paper we propose an efficient hybrid sorting method which takes advantage of wide vector registers and the high bandwidth memory of modern AVX-512-based multi-core and many-core processors. Our approach employs a combination of vectorized bitonic sorting and load-balanced multi-threaded merging. Thread-level and data-level parallelism are used to exploit both compute power and memory bandwidth. Our single-threaded implementation is ~30x faster than qsort in the C standard library and ~10x faster than C++'s std::sort. Compared with the Intel performance Primitives (IPP) library which is one of the most efficient CPU-based radix sort implementation, we obtain a speedup of 1.3 to 2.6. Furthermore, we achieve a peak performance of sorting 1.14 billion floats per second on a Xeon Phi 7210 processor. Moreover, we show the extensibility of our vectorized kernels to processing units with a varying of vector lanes. © 2019 IEEE.

关键词： Sorting

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An optimal profit route planning scheme based on ACO-OPP 21

An optimal profit route planning scheme based on ACO-OPP

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作者： Qiu, Yuhua Xu, Xiaolong Xia, Fei Jiangsu Key Laboratory of Big Data Security and Intelligent Processing Nanjing University of Posts and Telecommunications Nanjing China School of Computer Science Nanjing University of Posts and Telecommunications Nanjing China Information and communication Branch State Grid Jiangsu Electric Power Company Nanjing China

ISBN: (纸本)9781728120584

Taxi plays an important role of urban public transportation system. However, without appropriate route planning scheme, taxi drivers can only choose to wait or seek passengers in the absence of orders, leading to wasting a lot of time and fuel. In this paper, an optimal profit route planning scheme for taxi drivers with Ant Colony Optimization Algorithm based on Optimal Profit Points (ACO-OPP) is proposed. First, the taxi trajectory data are preprocessed and the pick-up and drop-off points are extracted to obtain high-quality data;second, the data spatiotemporal distribution is analyzed to plan a more appropriate and rational route;the clustering algorithm is used to obtain the optimal profit points to increase the occupancy rate of taxis;then, ACO-OPP is utilized to plan the profit routes for each taxi. A series of experiments are implemented based on the real taxi trajectory dataset to test and compare the performance of the simulated annealing algorithm, the genetic algorithm, the ant colony algorithm and ACO-OPP on the optimal route length and the profitability with the unit time profit function. The experimental results show that ACO-OPP has the shortest optimal route length and the best profit per unit time. © 2019 IEEE.

关键词： Profitability

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2D henon-chebyshev chaotic map for image encryption 21

2D henon-chebyshev chaotic map for image encryption

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作者： Qi, Fei Huang, Sijiang Li, Tong Yang, Haotian Kang, Xuejing School of Information and Communication Engineering Beijing University of Posts and Telecommunications China School of Computer Science Beijing University of Posts and Telecommunications China

ISBN: (纸本)9781728120584

Chaotic systems is widely employed in image encryption on account of its momentous properties including nonperiodicity, ergodicity, randomness and initial state sensitivity. However, some chaos-based cryptosystems still exhibit security problems due to the weak performance of their applied chaotic maps. To address those problems, a new two-dimensional HenonChebyshev map (2D-HCM) is first proposed in this paper. It is generated by connecting Henon map and Chebyshev map where the output of one map is used to adapt the input of the others. It results in a better chaotic performance in 2D-HCM, including better chaotic behaviors, higher chaotic index, wider chaotic range and finer ergodicity than other extant chaotic maps. Using the 2D-HCM, we further design an image encryption algorithm. The proposed algorithm disorganize the pixel positions of the input plain image with random sequence generated by 2D-HCM, and then convert it into DNA-planes using DNA operation rules. Finally, the cipher image is acquired by employing the newly defined DNA-level 2D cellular automata (DNA-CA) to update the DNA-planes in each iteration where 2D-HCM produces the rule number sequences applied in the update. Our scheme has proven to be highly efficient and secure by the experimental results and security analysis. © 2019 IEEE.

关键词： DNA

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Compressing encrypted images by using 2D compressed sensing 21

Compressing encrypted images by using 2D compressed sensing

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作者： Zhang, Bo Xiao, Di Zhang, Zhenyu Yang, Lei Communication NCO Academy Army Engineering University Chongqing China College of Computer Science Chongqing University Chongqing China

ISBN: (纸本)9781728120584

Compressing encrypted images by using compressed sensing (CS) has received more and more interests in recent years. However, the existing CS-based coding schemes for encrypted images cannot achieve the low computational complexity and high security at the same time. To address this problem, a novel image encryption-then-compression (ETC) system by using 2D CS (2DCS) is proposed in this paper. Firstly, for high security purpose, the entire image is encrypted by using global random permutation. Secondly, for low computational complexity purpose, the encrypted image is compressed by using 2DCS. Lastly, a 2D projected Landweber (2DPL) algorithm is proposed for image reconstruction. Compared with the state-of-the-art CS-based ETC methods, it has two advantages. Firstly, it achieves the low computational complexity and high security at the same time. Secondly, it obtains a significant gain of peak signal-to-noise ratio (PSNR) of the reconstructed-images. © 2019 IEEE.

关键词： Compressed sensing

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Exploring cascaded write amplification in LSM-tree based key-value stores with solid-state disks 21

Exploring cascaded write amplification in LSM-tree based key...

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作者： Sun, Hui Dai, Shangshang Huang, Jianzhong Key Laboratory of Intelligent Computing and Signal Processing Ministry of Education School of Computer Sci. and Tech. Anhui University Hefei China Wuhan National Lab. for Optoelectronics Huazhong University of Sci. and Tech Wuhan China

ISBN: (纸本)9781728120584

Log-structured merge tree (i.e., LSM-tree) based key-value stores, which are widely used in big-data applications, provide high performance. NAND Flash-based Solid state disks (i.e., SSDs) become the popular devices that alternative to hard disk drives (i.e., HDDs) because of the high performance and low power consumption. LSM-tree KV stores with SSDs are deployed in large-scale storage systems to achieve high performance in the cloud. However, the host-side write amplification in LSM-tree KV stores and the device-side write amplification in SSDs can impair the overall system performance. The former that is attributed to compaction has a burn on I/O bandwidth between two sides. The latter, which results from garbage collection in NAND Flash memory, blocks user I/Os from the host and degrades the SSD performance. In this study, we explored cascaded write amplification in LSM-tree KV stores with SSDs. Our primary goal is to comprehensively study two-level cascaded write amplification on the host and device sides. We quantitatively analyze the impact of two-level write amplification on overall performance. This work reveals details of cascaded write amplification and helps developers in the software stacks of LSM-tree based KV stores with SSDs. © 2019 IEEE.

关键词： NAND circuits

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Attitude estimation algorithm of abnormal gait recognition with dynamic step conjugate gradient 21

Attitude estimation algorithm of abnormal gait recognition w...

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作者： Gao, Jing Gu, Peishang Ren, Qing Song, Xin School of Control Engineering Northeastern University China School of Computer and Communication Engineering Northeastern University Qinhuangdao China

ISBN: (纸本)9781728120584

In this paper, a conjugate gradient hybrid filtering fusion algorithm for multi-sensor data fusion is proposed to solve the problems of gyroscope drift and cumulative error in gait analysis system based on inertial sensors. The algorithm improves the attitude resolution algorithm for abnormal gait recognition effectively. A conjugate gradient optimization algorithm with dynamic step length is proposed to solve the problem that the traditional conjugate gradient algorithm can only tackle the problem of the settlement accuracy under the constant motion rate. The step length is proportional to the actual physical angular velocity length of human motion, which meets the requirements of abnormal gait recognition under different motion rates. As for the problem of the inaccurate attitude calculation angle caused by motion acceleration generated from the non-uniformity of human motion, a motion acceleration suppression algorithm is proposed, which separates the gravity acceleration from motion acceleration to improve the accuracy of the gait analysis system. By comparing this fusion algorithm of conjugate gradient hybrid filter with other algorithms, we can conclude that the proposed algorithm can reduce the accumulated error of gyroscope and the interference of motion acceleration on the solution accuracy and improve the static performance and dynamic performance of the abnormal gait recognition system effectively. © 2019 IEEE.

关键词： Gyroscopes

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