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检索条件"任意字段=21st International Symposium on Computer Architecture and High Performance Computing"

共 1770 条记录，以下是71-80 订阅

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Understanding GPU Errors on Large-scale HPC Systems and the Implications for System Design and Operation 21

Understanding GPU Errors on Large-scale HPC Systems and the ...

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IEEE 21st international symposium on high performance computer architecture (HPA)

作者： Tiwari, Devesh Gupta, Saurabh Rogers, James Maxwell, Don Rech, Paolo Vazhkudai, Sudharshan Oliveira, Daniel Londo, Dave DeBardeleben, Nathan Navaux, Philippe Carro, Luigi Bland, Arthur Cray Inc Seattle WA USA Los Alamos Natl Lab Los Alamos NM USA Univ Fed Rio Grande do Sul BR-90046900 Porto Alegre RS Brazil Oak Ridge Natl Lab Oak Ridge Leadership Comp Facil Oak Ridge TN 37831 USA

ISBN: (纸本)9781479989300

Increase in graphics hardware performance and improvements in programmability has enabled GPUs to evolve from a graphics-specific accelerator to a general-purpose computing device. Titan, the world's second fastest supercomputer for open science in 2014, consists of more than 18,000 GPUs that scientists from various domains such as astrophysics, fusion, climate, and combustion use routinely to run large-scale simulations. Unfortunately, while the performance efficiency of GPUs is well understood, their resilience characteristics in a large-scale computing system have not been fully evaluated. We present a detailed study to provide a thorough understanding of GPU errors on a large-scale GPU-enabled system. Our data was collected from the Titan supercomputer at the Oak Ridge Leadership computing Facility and a GPU cluster at the Los Alamos National Laboratory. We also present results from our extensive neutron-beam tests, conducted at Los Alamos Neutron Science Center (LANSCE) and at ISIS (Rutherford Appleton Laboratories, UK), to measure the resilience of different generations of GPUs. We present several findings from our field data and neutron-beam experiments, and discuss the implications of our results for future GPU architects, current and future HPC computing facilities, and researchers focusing on GPU resilience.

关键词： GRAPPER PICK UP Graphics Processing Unit Resilience Los Alamos National Laboratory high performance computing programmability supercomputer graphic images Titan

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high performance Serverless architecture for Deep Learning Workflows 21

High Performance Serverless Architecture for Deep Learning W...

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21st IEEE/ACM international symposium on Cluster, Cloud and Internet computing (CCGrid)

作者： Chahal, Dheeraj Ramesh, Manju Ojha, Ravi Singhal, Rekha TCS Res Mumbai Maharashtra India

ISBN: (纸本)9781728195865

Serverless architecture is a rapidly growing paradigm for deploying deep learning applications performing ephemeral computing and serving bursty workloads. Serverless architecture promises automatic scaling and cost efficiency for inferencing deep learning models while minimizing the operational logic. However, serverless computing is stateless with constraints on local resources. Hence, deploying complex deep learning applications containing large size models, frameworks, and libraries is a challenge. In this work, we discuss a methodology and architecture for migrating deep vision algorithms and model based applications to a serverless computing platform. We have tested our methodology using AWS infrastructure (AWS Lambda, Provisioned Concurrency, VPC endpoint, S3 and EFS) to mitigate the challenges in deploying composition of APIs containing large deep learning models and frameworks. We evaluate the performance and cost of our architecture for a real-life enterprise application used for document processing.

关键词： Serverless FaaS Cloud AI

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SNNAP: Approximate computing on Programmable SoCs via Neural Acceleration 21

SNNAP: Approximate Computing on Programmable SoCs via Neural...

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IEEE 21st international symposium on high performance computer architecture (HPA)

作者： Moreau, Thierry Wyse, Mark Nelson, Jacob Sampson, Adrian Esmaeilzadeh, Hadi Ceze, Luis Oskin, Mark Univ Washington Seattle WA 98195 USA Georgia Inst Technol Atlanta GA 30332 USA

ISBN: (纸本)9781479989300

Many applications that can take advantage of accelerators are amenable to approximate execution. Past work has shown that neural acceleration is a viable way to accelerate approximate code. In light of the growing availability of on-chip field-programmable gate arrays (FPGAs), this paper explores neural acceleration on off-the-shelf programmable SoCs. We describe the design and implementation of SNNAP, a flexible FPGA-based neural accelerator for approximate programs. SNNAP is designed to work with a compiler workflow that configures the neural network's topology and weights instead of the programmable logic of the FPGA itself. This approach enables effective use of neural acceleration in commercially available devices and accelerates different applications without costly FPGA reconfigurations. No hardware expertise is required to accelerate software with SNNAP, so the effort required can be substantially lower than custom hardware design for an FPGA fabric and possibly even lower than current "C-to-gates" high-level synthesis (HLS) tools. Our measurements on a Xilinx Zynq FPGA show that SNNAP yields a geometric mean of 3.8xspeedup (as high as 38.1x) and 2.8x energy savings (as high as 28x) with less than 10% quality loss across all applications but one. We also compare SNNAP with designs generated by commercial HLS tools and show that SNNAP has similar performance overall, with better resource-normalized throughput on 4 out of 7 benchmarks.

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SELFWATTS: On-the-fly Selection of performance Events to Optimize Software-defined Power Meters 21

SELFWATTS: On-the-fly Selection of Performance Events to Opt...

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21st IEEE/ACM international symposium on Cluster, Cloud and Internet computing (CCGrid)

作者： Fieni, Guillaume Rouvoy, Romain Seiturier, Lionel Univ Lille INRIA Lille France IUF Lille France

ISBN: (纸本)9781728195865

Fine-grained power monitoring of software-defined infrastructures is unavoidable to maximize the power usage efficiency of data centers. However, the design of the underlying power models that estimate the power consumption of the monitored software components keeps being a long and fragile process that remains tightly coupled to the host machine and prevents a wider adoption by the industry beyond the rich literature on this topic. To overcome these limitations, this paper introduces SELFWATTS: a lightweight power monitoring system that explores and selects the relevant performance events to automatically optimize the power models to the underlying architecture. Unlike state-of-the-art techniques, SELFWATTS does not require any a priori training phase or specific hardware to configure the power models and can be deployed on a wide range of machines, including heterogeneous environments.

关键词： Meters Training Data centers Power demand computer architecture Production Containers

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architecture AND EVALUATION OF A high-SPEED NETWORKING SUBSYstEM FOR DIstRIBUTED-MEMORY SYstEMS

ARCHITECTURE AND EVALUATION OF A HIGH-SPEED NETWORKING SUBSY...

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21st Annual international symposium on computer architecture

作者： stEENKIstE, P HEMY, M MUMMERT, T ZILL, B CARNEGIE MELLON UNIV SCH COMP SCIPITTSBURGHPA 15213

ISBN: (纸本)0818655100

Achieving high-speed network I/O on distributed-memory systems is difficult because their architecture is in general ill-suited for communication processing. Some of the common problems are: inability to do protocol processing, inefficient handling of data distribution, and poor management of the I/O. In this paper we present an I/O architecture that addresses these problems and supports high-speed network I/O on distributed-memory systems. The key to good performance is to partition the work appropriately between the system and the network interface. We perform some communication tasks on the distributed-memory parallel system since it is more powerful, and less likely to become a bottleneck than the network interface. Tasks that do not parallelize well are performed on the network interface and hardware support is provided for the most time-critical operations. We emphasize the use of simple I/O mechanisms that can be used by programming tools that map applications on the distributed-memory system to implement efficient I/O for the class of applications they support. This architecture has been implemented for the iWarp distributed-memory system. We describe this implementation and present performance results.

关键词： computer architecture

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high performance computing for the science of 21st century

High performance computing for the science of 21st century

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IEEE John Vincent Atanasoff international symposium on Modern computing

作者： Erbacci, Giovanni CINECA High Performance Syst Div I-40033 Bologna Italy

ISBN: (纸本)0769526438

A picture of the state of the art of the HPC architectures at the service of computational sciences is presented, and the need for computational infrastructures to enhance support to scientific research is underlined. After this general overview, HPC-Europa a successful example of a computational infrastructure at the service of science at European level, is presented and the objectives are highlighted.

关键词： Natural sciences computing

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Proceedings - 21st Annual international IEEE symposium on Field-Programmable Custom computing Machines, FCCM 2013

Proceedings - 21st Annual International IEEE Symposium on Fi...

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21st Annual international IEEE symposium on Field-Programmable Custom computing Machines, FCCM 2013

The proceedings contain 49 papers. The topics discussed include: Minerva: accelerating data analysis in next-generation SSDs;accelerating join operation for relational databases with FPGAs;boosting memory performance of many-core FPGA device through dynamic precedence graph;acceleration of SQL restrictions and aggregations through FPGA-based dynamic partial reconfiguration;accuracy-performance tradeoffs on an FPGA through overclocking;safe overclocking of tightly coupled CGRAs and processor arrays using razor;escaping the academic sandbox: realizing VPR circuits on Xilinx devices;a case for heterogeneous technology-mapping: soft versus hard multiplexers;accurate thermal-profile estimation and validation for FPGA-mapped circuits;on-chip context save and restore of hardware tasks on partially reconfigurable FPGAs;a reconfigurable architecture for 1-D and 2-D discrete wavelet transform;and high speed video processing using fine-grained processing on FPGA platform.

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An edge computing architecture in the Internet of Things 21

An edge computing architecture in the Internet of Things

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21st IEEE international symposium on Real-Time computing (ISORC)

作者： Martin, Cristian Diaz, Manuel Rubio, Bartolome Univ Malaga Dept Languages & Comp Sci Malaga Spain

ISBN: (纸本)9781538658475

In the last few years, the Internet of Things (IoT) has emerged as the new disruptive technology to change the world. Cloud computing has accompanied this field to overcome its processing and storage limitations. However, this evolution has originated a huge increase in IoT devices and data that will create a bottleneck for current networks, in addition to a lack of low latency in cloud communications. Edge computing has been developed to address this challenge, moving the processing to the edge of the network. In this paper, an edge computing architecture is presented to overcome these challenges. The architecture, based on our previous work on the lambda-CoAP architecture, covers the whole vision of an edge computing deployment, from IoT devices, to the edge Smart Gateways and up to a cloud infrastructure.

关键词： computer architecture Cloud computing Logic gates Containers Edge computing Virtualization Real-time systems"

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Bamboo ECC: strong, Safe, and Flexible Codes for Reliable computer Memory 21

Bamboo ECC: Strong, Safe, and Flexible Codes for Reliable Co...

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IEEE 21st international symposium on high performance computer architecture (HPA)

作者： Kim, Jungrae Sullivan, Michael Erez, Mattan Univ Texas Austin Dept Elect & Comp Engn Austin TX 78712 USA

ISBN: (纸本)9781479989300

Growing computer system sizes and levels of integration have made memory reliability a primary concern, necessitating strong memory error protection. As such, large-scale systems typically employ error checking and correcting codes to trade redundant storage and bandwidth for increased reliability. While stronger memory protection will be needed to meet reliability targets in the future, it is undesirable to further increase the amount of storage and bandwidth spent on redundancy. We propose a novel family of single-tier ECC mechanisms called Bamboo ECC to simultaneously address the conflicting requirements of increasing reliability while maintaining or decreasing error protection overheads. Relative to the state-of-the-art single-tier error protection, Bamboo ECC codes have superior correction capabilities, all but eliminate the risk of silent data corruption, and can also increase redundancy at a fine granularity, enabling more adaptive graceful downgrade schemes. These strength, safety, and flexibility advantages translate to a significantly more reliable memory system. To demonstrate this, we evaluate a family of Bamboo ECC organizations in the context of conventional 72b and 144b DRAM channels and show the significant error coverage and memory lifespan improvements of Bamboo ECC relative to existing SEC-DED, chipkill-correct and double-chipkill-correct schemes.

关键词： Error correction codes Elliptic curve cryptography EMERGENCY CONTROL CENTERS computer memory data corruption error protection redundancy bamboos Bandwidth error checking store protection Fine Grain Size Cache Memory System one layer Codes

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QoS-based network service broker for high-performance grid applications

QoS-based network service broker for high-performance grid a...

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21st international Conference on Advanced Networking and Applications

作者： Duan, Qiang Talley, Michelle Seetha, Neeta Univ Cent Arkansas Dept Comp Sci Conway AR 72035 USA

ISBN: (纸本)9780769528465

Grid computing is an emerging computing paradigm that will have a significant impact on the next generation information infrastructure. computer networks and the Grid should be integrated together for supporting high-performance applications and a QoS-based network service broker is the key to this integration. In this paper we propose a new approach for describing QoS capabilities of network services and develop a QoS-based broker technology for selecting network services that meet QoS requirements of Grid applications. Our approach for network service description and selection is highly flexible and applicable to networking systems with various implementations. We also propose a system architecture for realizing the QoS-based network service broker within the service-oriented Grid architecture.

关键词： Grid computing

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