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检索条件"任意字段=21st International Symposium on Computer Architecture and High Performance Computing"

共 1770 条记录，以下是81-90 订阅

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A Reconfigurable architecture for 1-D and 2-D Discrete Wavelet Transform

A Reconfigurable Architecture for 1-D and 2-D Discrete Wavel...

引用

21st Annual international IEEE symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Sun, Qing Jiang, Jiang Zhu, Yongxin Fu, Yuzhuo Shanghai Jiao Tong Univ Sch Microelect Shanghai 200030 Peoples R China

ISBN: (纸本)9780769549699;9781467360050

In this paper, we propose a novel architecture for DWT that can be reconfigured to be adapted to different kinds of filter banks and different sizes of inputs. high flexibility and generality are achieved by using the MAC loop based filter(MLBF). Classic methods, such as polyphase structure and fragment-based sample consumption, are used to enhance the parallelism of the system. The architecture can be reconfigured to 3 modes to deal with 1-D or 2-D DWT with different bandwidth and throughput requirements.

关键词： DWT reconfigurable FPGA implementation pipeline architecture high flexibility

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The Impact of Hardware Communication on a Heterogeneous computing System

The Impact of Hardware Communication on a Heterogeneous Comp...

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21st Annual international IEEE symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Gao, Shanyuan Huang, Bin Sass, Ron Univ N Carolina Reconfigurable Comp Syst Lab Charlotte NC 28223 USA

ISBN: (纸本)9780769549699;9781467360050

This paper designed a MPI-like Message Passing Engine (MPE) as part of the on-chip network, providing point-to-point and collective communication primitives in hardware. On one hand, the MPE offloads the communication workload from the general processing elements. On the other hand, the MPE provides direct interface to the heterogeneous processing elements which can eliminate the data path going around the OS and libraries. The experimental results have shown that the MPE can significantly reduce the communication time and improve the overall performance, especially for heterogeneous computing systems.

关键词： MPE gene channels (data transmission) computer hardware network-on-chip Communication Research Processing Element osmium

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Experimental evaluation of emerging multi-core architectures

Experimental evaluation of emerging multi-core architectures

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21st international Parallel and Distributed Processing symposium, IPDPS 2007

作者： Kayi, Abdullah Yao, Yiyi El-Ghazawi, Tarek Newby, Greg George Washington University Dept. of Electrical and Computer Engineering Washington DC 20052 United States Arctic Region Supercomputing Center Fairbanks AK 99775 United States

ISBN: (纸本)1424409101

The trend of increasing speed and complexity in the single-core processor as stated in the Moore's law is facing practical challenges. As a result, the multi-core processor architecture has emerged as the dominant architecture for both desktop and high-performance systems. Multi-core systems introduce many challenges that need to be addressed to achieve the best performance. Therefore, a new set of benchmarking techniques to study the impacts of the multi-core technologies is necessary. In this paper, multi-core specific performance metrics for cache coherency and memory bandwidth/latency/contention are investigated. This study also proposes a new benchmarking suite which includes cases extended from the high performance computing Challenge (HPCC) benchmark suite. performance results are measured on a Sun Fire T1000 server with six cores and an AMD Opteron dual core system. Experimental analysis and observations in this paper provide for a better understanding of the emerging multi-core architectures. © 2007 IEEE.

关键词： computer architecture

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TreeNet: A Hierarchical Deep Learning Model to Facilitate Edge Intelligence for Resource-Constrained Devices 21

TreeNet: A Hierarchical Deep Learning Model to Facilitate Ed...

引用

21st IEEE/ACM international symposium on Cluster, Cloud and Internet computing (CCGrid)

作者： Lu, Dong Zhai, Yanlong Wu, Jianqing Shen, Jun Beijing Inst Technol Sch Comp Sci Beijing Peoples R China Univ Wollongong Sch Comp & Informat Technol Wollongong NSW Australia

ISBN: (纸本)9781728195865

Deep learning has achieved remarkable successes in various areas such as computer vision and natural language processing. Many sophisticated models have been proposed to improve performance by designing a significant number of layers of neurons. As an emerging research area, edge intelligence tries to bring intelligence to the network edge by integrating edge computing and AI technologies and it has gained wide attention for its lower latency and better privacy preservation features. Nevertheless, training and inferencing deep neural networks require intensive computation power and time, making it quite challenging to run the models on the resource-constrained edge devices. In this paper, we propose a deep learning model, namely TreeNet, based on task decomposition. After obtaining a task, we would not fit the entire task but decompose the task into disjoint sub-tasks to reduce the complexity of the required deep learning model (it could be divided multiple times if necessary). We first fit the original dataset mapping to different sub-tasks and then fit the mapping of each sub-task to the category of the original dataset that it contains. During the running of the model, we dynamically call the low-level classifier based on the inference result of the high-level classifier. When the inference result of the high-level classifier is unreliable, we send the input sample to the cloud server for processing. We use several popular datasets to study the TreeNet architecture and show that it can process most of the input data while achieving high inference accuracy and significantly decreasing the total amount of calculation.

关键词： edge computing deep learning resource-constrained model compression model acceleration edge intelligence

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ParalleX: A study of a new parallel computation model

ParalleX: A study of a new parallel computation model

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21st international Parallel and Distributed Processing symposium, IPDPS 2007

作者： Gao, Guang R. sterling, Thomas stevens, Rick Hereld, Mark Zhu, Weirong Department of Electrical and Computer Engineering University of Delaware Center for Advanced Computing Research California Institute of Technology Department of Computer Science Louisiana State University Mathematics and Computer Science Division Argonne National Laboratory

ISBN: (纸本)1424409101

This paper proposes the study of a new computation model that attempts to address the underlying sources of performance degradation (e.g. latency, overhead, and starvation) and the difficulties of programmer productivity (e.g. explicit locality management and scheduling, performance tuning, fragmented memory, and synchronous global barriers) to dramatically enhance the broad effectiveness of parallel processing for high end computing. In this paper, we present the progress of our research on a parallel programming and execution model - mainly, ParalleX. We describe the functional elements of ParalleX, one such model being explored as part of this project. We also report our progress on the development and study of a subset of ParalleX - the LITL-X at University of Delaware. We then present a novel architecture model - Gilgamesh II - as a ParalleX processing architecture. A design point study of Gilgamesh II and the architecture concept strategy are presented. © 2007 IEEE.

关键词： Parallel processing systems

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The Effect of Compiler Optimizations on high-Level Synthesis for FPGAs

The Effect of Compiler Optimizations on High-Level Synthesis...

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21st Annual international IEEE symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Huang, Qijing Lian, Ruolong Canis, Andrew Choi, Jongsok Xi, Ryan Brown, stephen Anderson, Jason Univ Toronto Dept Elect & Comp Engn Toronto ON Canada

ISBN: (纸本)9780769549699;9781467360050

We consider the impact of compiler optimizations on the quality of high-level synthesis (HLS)-generated FPGA hardware. Using a HLS tool implemented within the state-of-the-art LLVM [1] compiler, we study the effect of compiler optimizations on the hardware metrics of circuit area, execution cycles, Fmax, and wall-clock time. We evaluate 56 different compiler optimizations implemented within LLVM and show that some optimizations significantly affect hardware quality. Moreover, we show that hardware quality is also affected by the order in which optimizations are applied. We then present a new HLS-directed approach to compiler optimizations, wherein we execute partial HLS and profiling at intermittent points in the optimization process and use the results to judiciously undo the impact of optimization passes predicted to be damaging to the generated hardware quality. Results show that our approach produces circuits with 16% better speed performance, on average, versus using the standard -O3 optimization level.

关键词： FPGAs high-level synthesis algorithms compilers computer-aided design performance

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Software Rejuvenation Schemes for Time Warp-based PDES 21

Software Rejuvenation Schemes for Time Warp-based PDES

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IEEE 21st Pacific Rim international symposium on Dependable computing (PRDC 2015)

作者： Fukumoto, Satoshi Ohara, Mamoru Tokyo Metropolitan Univ Fac Syst Design Hino Tokyo 1910065 Japan Tokyo Metropolitan Ind Technol Res Inst Koto Tokyo 1350064 Japan

ISBN: (纸本)9781467393768

Software rejuvenation is a technique to prevent the aging of running software. Recently, benefits of software rejuvenation in high-performance computing (HPC) areas have received attention. In time warp-based parallel discrete event simulation (PDES) systems, it is important to improve performance to equalize simulation progress in processes. In this article, we consider a number of schemes for time warp-based PDES to avoid the imbalance simulation progress introduced by rejuvenation.

关键词： software rejuvenation high-performance computing parallel discrete event simulation (PDES) time warp

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Benchmarking Serverless Workloads on Kubernetes 21

Benchmarking Serverless Workloads on Kubernetes

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21st IEEE/ACM international symposium on Cluster, Cloud and Internet computing (CCGrid)

作者： Govind, Hima Gonzalez-Velez, Horacio Natl Coll Ireland Cloud Competency Ctr Dublin Ireland

ISBN: (纸本)9781728195865

As a disruptive paradigm in the cloud landscape, Serverless computing is attracting attention because of its unique value propositions to reduce operating costs and outsource infrastructure management. Nevertheless, enterprise Function-as-a-Service (FaaS) platforms may pose significant risks such as vendor lock-in, lack of security control due to multi-tenancy, complicated pricing models, and legal and regulatory compliance-particularly in mobile computing scenarios. This work proposes a production-grade fault-tolerant serverless architecture based on a highly-available Kubernetes topology using an open-source framework, deployed on Openstack instances, and benchmarked with a realistic scaled-down Azure workload traces dataset. By measuring success rate, throughput, latency, and auto scalability, we have managed to assess not only resilience but also sustained performance under a logistic model for three distinct representative workloads. Our test executions show, with 95%-confidence, that between 70 and 90 concurrent users can access the system while experiencing acceptable performance. Beyond the breaking point identified (i.e. 91 transactions per second), the Kubernetes cluster has to be scaled-up or scaled out to meet the QoS and availability requirements.

关键词： Serverless OpenFaas high Availability Workload modelling Service Level Agreement SLA Mobile computing Azure Containers

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high performance java sockets for parallel computing on clusters

High performance java sockets for parallel computing on clus...

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21st international Parallel and Distributed Processing symposium, IPDPS 2007

作者： Taboada, Guillermo L. Touriño, Juan Doallo, Ramón Computer Architecture Group Dept. of Electronics and Systems University of A Coruña A Coruña 15071 Spain

ISBN: (纸本)1424409101

The use of Java for parallel programming on clusters relies on the need of efficient communication middleware and high-speed cluster interconnect support. Nevertheless, currently there are no solutions that fully fulfill these issues. In this paper, a Java sockets library has been tailored to increase the efficiency of Java parallel applications on clusters. This library supports high-speed cluster interconnects and its API has been extended to meet the requirements of a high performance Java RMI implementation and Java parallel applications on clusters. Thus, it provides Java with a more efficient communication middleware on clusters. The performance evaluation of this middleware on a Gigabit Ethernet (GbE) and a Scalable Coherent Interface (SCI) cluster has shown experimental evidence of throughput increase. Moreover, qualitative aspects of the solution such as transparency to the user, interoperability with other systems and no need of source code modifications are decisive to boost the performance of existing Java parallel applications and their developments in high performance Java cluster computing. © 2007 IEEE.

关键词： Parallel processing systems

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An Evaluation of high-performance Embedded Processing on MPPAs

An Evaluation of High-Performance Embedded Processing on MPP...

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21st Annual international IEEE symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Zain-ul-Abdin Svensson, Bertil Halmstad Univ Halmstad Sweden

ISBN: (纸本)9780769549699;9781467360050

Embedded signal processing is facing the challenges of increased performance as well as to achieve energy efficiency. Massively parallel processor arrays (MPPAs) consisting of tens or hundreds of processing cores offer the possibility of meeting the growing performance demand in an energy efficient way by exploiting parallelism instead of scaling the clock frequency of a single powerful processor. In this paper, we evaluate two variants of MPPAs by implementing a significantly large case study, namely an auto focus criterion calculation, which is a key component in modern synthetic aperture radar systems. The implementation results from the two target architectures are compared on the basis of utilized resources, performance, and energy efficiency. The Ambric implementations demonstrate the usefulness of occampibased high-level language approach in utilizing hundreds of processors, whereas the Epiphany implementation reveals that energy-efficiency can be improved even further by a factors of 2-3 with respect to the Ambric implementations and can be achieved at high clock speeds.

关键词： Energy efficiency PROCESSOR clock frequency high-performance embedding massively parallel processors signal processing Crucial components high level language(hll) Radar systems

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