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Euro-Par Conference / 7th international Workshop on Programming Models and Applications for Multicores and Manycores (PMAM) held in conjunction with the 21st SIGPLAN symposium on Principles and Practice of Parallel Programming (PPoPP)

作者： Muyan-Ozcelik, Pinar Owens, John D. Calif State Univ Sacramento Sacramento CA 95819 USA Univ Calif Davis Davis CA 95616 USA

In this study, we provide an extensive survey on wide spectrum of scheduling methods for multitasking among graphics processing unit (GPU) computing tasks. We then design several schedulers and explain in detail the selected methods we have developed to implement our scheduling strategies. Next, we compare the performance of schedulers on various workloads running on Fermi and Kepler architectures and arrive at the following major conclusions: (1) Small kernels benefit from running kernels concurrently. (2) The combination of small kernels, high-priority kernels with longer runtimes, and lower-priority kernels with shorter runtimes benefits from a CPU scheduler that dynamically changes kernel order on the Fermi architecture. (3) Because of limitations of existing GPU architectures, currently CPU schedulers outperform their GPU counterparts. We also provide results and observations obtained from implementing and evaluating our schedulers on the NVIDIA Jetson TX1 system-on-chip architecture. We observe that although TX1 has the newer Maxwell architecture, the mechanism used for scheduler timings behaves differently on TX1 compared to Kepler leading to incorrect timings. In this paper, we describe our methods that allow us to report correct timings for CPU schedulers running on TX1. Finally, we propose new research directions involving the investigation of additional scheduling strategies.

关键词： GPU computing multitasking real-time embedded tasks

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Network-centric supervisory control system for mobile robotic groups 12th

Network-centric supervisory control system for mobile roboti...

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12th international symposium on Intelligent Systems (INTELS)

作者： Muliukha, Vladimir Ilyashenko, Alexander Laboshin, Leonid Peter Great St Petersburg Polytech Univ 29 Polytechnicheskaya St St Petersburg 195251 Russia Russian State Sci Ctr Robot & Tech Cybernet Tikhoretsky Prospect 21 St Petersburg 194064 Russia

The paper analyzes network-centric control methods for mobile robotic groups. We consider the task of controlling a group of mobile robots, performing reconnaissance for space and terrestrial applications. In the paper each robot is a cyber-physical object consisting of mechatronic part and computer module, which analyzes data from sensors and generates commands. The use of network-centric approach allows separating these two parts, transferring resource-intensive computing tasks in a high-performance hybrid cloud environment. A cloud environment as a single point for processing of all sensory data allows us to use the advantages of centralized control method and to manage the resources of mobile robots more effectively. In this case, each robot keeps the autonomy if there is no communication with the control center. So a key element of such control systems is reliable communication links. In our work we use redundancy and duplication of various communication channels to provide a continuous connection between a mobile robot and control center. (C) 2017 The Authors. Published by Elsevier B.V.

关键词： network-centric control system cyber-physical approach mobile robots high-performance cloud system

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Fog computing and Its Role in Development of Smart Applications

Fog Computing and Its Role in Development of Smart Applicati...

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IEEE international Conference on Big Data and Cloud computing (BdCloud)

作者： Mandeep Kaur Saroa Rajni Aron Lovely Professional University Phagwara Punjab IN Department of CSE Lovely Professional University Punjab India

ISBN: (纸本)9781728111421;9781728111414

In 21st century, Internet of Things (IoT) is playing an important role in developing Smart cities. With the growth of IoT, data is growing with acceleration. As the data is growing the need to store data is also increasing. More the data, the latency will be high to store and retrieve data from the cloud. The concept of fog computing was originated to diminish the latency for accessing the data to and from the cloud. Fog computing imparts the storage, computing as well as networking services at the end point of the network. Fog nodes also have limited computational capabilities. Due to some weaknesses, fog computing and cloud computing cannot sustain alone, so both these technologies are integrated to build smart IoT infrastructure for Smart city. Fog computing have a major role and supreme responsibility in development of a Smart city. This paper discusses various applications of fog computing and their implementations in a Smart cities. It also proposes a prototype for Waste management system in a city. Fog computing can help to govern the waste collection of the city in a smart way. On the basis of our review, several open concerns and challenges of fog computing are discussed, and the directions for future researchers have also been discussed.

关键词： Edge computing Cloud computing computer architecture Internet of Things Sensors Security Smart cities

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Two-level main memory co-design: Multi-threaded algorithmic primitives, analysis, and simulation

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JOURNAL OF PARALLEL AND DIstRIBUTED computing 2017年 102卷 213-228页

作者： Bender, Michael A. Berry, Jonathan W. Hammond, Simon D. Hemmert, K. Scott McCauley, Samuel Moore, Branden Moseley, Benjamin Phillips, Cynthia A. Resnick, David Rodrigues, Arun SUNY Stony Brook Comp Sci Stony Brook NY 11794 USA SUNY Stony Brook Stony Brook NY 11794 USA Sandia Natl Labs Ctr Res Comp POB 5800 Albuquerque NM 87185 USA Washington Univ Dept Comp Sci St Louis MO 63130 USA Washington Univ Dept Engn St Louis MO 63130 USA

A challenge in computer architecture is that processors often cannot be fed data from DRAM as fast as CPUs can consume it. Therefore, many applications are memory-bandwidth bound. With this motivation and the realization that traditional architectures (with all DRAM reachable only via bus) are insufficient to feed groups of modern processing units, vendors have introduced a variety of non-DDR 3D memory technologies (Hybrid Memory Cube (HMC),Wide I/O 2, high Bandwidth Memory (HBM)). These offer higher bandwidth and lower power by stacking DRAM chips on the processor or nearby on a silicon interposer. We will call these solutions "near-memory," and if user-addressable, "scratchpad." high-performance systems on the market now offer two levels of main memory: near-memory on package and traditional DRAM further away. In the near term we expect the latencies near-memory and DRAM to be similar. Thus, it is natural to think of near-memory as another module on the DRAM level of the memory hierarchy. Vendors are expected to offer modes in which the near memory is used as cache, but we believe that this will be inefficient. In this paper, we explore the design space for a user-controlled multi-level main memory. Our work identifies situations in which rewriting application kernels can provide significant performance gains when using near-memory. We present algorithms designed for two-level main memory, using divide and-conquer to partition computations and streaming to exploit data locality. We consider algorithms for the fundamental application of sorting and for the data analysis kernel k-means. Our algorithms asymptotically reduce memory-block transfers under certain architectural parameter settings. We use and extend Sandia National Laboratories' Sst simulation capability to demonstrate the relationship between increased bandwidth and improved algorithmic performance. Memory access counts from simulations corroborate predicted performance improvements for our sorting algor

关键词： Two-level memory high-bandwidth memory Sorting k-means clustering

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21st international symposium on VLSI Design and Test, VDAT 2017

21st International Symposium on VLSI Design and Test, VDAT 2...

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21st international symposium on VLSI Design and Test, VDAT 2017

ISBN: (纸本)9789811074691

The proceedings contain 75 papers. The special focus in this conference is on VLSI Design and Test. The topics include: An improved highly efficient low input voltage charge pump circuit;A calibration technique for current steering DACs - Self calibration with capacitor storage;characterization and compensation circuitry for piezo-resistive pressure sensor to accommodate temperature induced variation;FEM based device simulator for high voltage devices;Synapse circuits implementation and analysis in 180 nm MOSFET and CNFET technology;A 10 MHz, 73 ppm/°C, 84 µw PVT compensated ring oscillator;deterministic shift power reduction in test compression;Pseudo-BIst: A novel technique for SAR-ADC testing;SFG based fault simulation of linear analog circuits using fault classification and sensitivity analysis;estimating the maximum propagation delay of 4-bit ripple carry adder using reduced input transitions;a cost effective technique for diagnosis of scan chain faults;multi-mode toggle random access scan to minimize test application time;performance analysis of disability based fault tolerance techniques for permanent faults in chip multiprocessors;Low-power sequential circuit design using work-function engineered FinFETs;Vertical nanowire FET based standard cell design employing Verilog-A compact model for higher performance;analysis of electrolyte-insulator-semiconductor tunnel field-effect transistor as pH sensor;Exploiting characteristics of steep slope tunnel transistors towards energy efficient and reliable buffer designs for IoT SoCS;An efficient VLSI architecture for PRESENT block cipher and its FPGA implementation;Investigation of TCADs models for characterization of sub 16 nm in In0.53Ga0.47As FinFET;hausdorff distance driven L-shape matching based layout decomposition for E-beam lithography.

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Design & Development of high Speed LVDS Receiver with Cold-Spare Feature in SCL's 0.18 μm CMOS Process 21st

Design & Development of High Speed LVDS Receiver with Cold-S...

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21st international symposium on VLSI Design and Test (VDAT)

作者： Malik, Munish Kumar, Ajay Jatana, H. S. Semicond Lab Mohali India

ISBN: (纸本)9789811074707;9789811074691

This paper presents design and implementation of LVDS Receiver chip in SCL's CMOS 0.18 mu m, 3.3 V process. It is compatible with Low Voltage Differential Signaling (LVDS) standard. The receiver is designed for data rate of 1Gbps. This chip consists of four channels of LVDS receiver. The size of the chip is 2130 mu m x 1500 mu m and is packaged in 16 pin CFP (ceramic flat pack) package. The chip architecture, design, measured results are presented here. The radiation test such as total ionizing dose (TID) upto 300 K rad is performed on chip and single event effects (SEE) test using heavy ions Nickel (Ni-58) and Silver (Ag-107) has also been carried out. The performance under radiation environment is also been given.

关键词： CMOS LVDS Radiation Coldspare SEE TID

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RCube: A Power Efficient and highly Available Network for Data Centers 31

RCube: A Power Efficient and Highly Available Network for Da...

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31st IEEE international Parallel and Distributed Processing symposium (IPDPS)

作者： Li, Zhenhua Yang, Yuanyuan SUNY Stony Brook Dept Elect & Comp Engn Stony Brook NY 11794 USA

ISBN: (纸本)9781538639146

Designing a cost-effective network for data centers that can deliver sufficient bandwidth and provide high availability has drawn tremendous attentions recently. In this paper, we propose a novel server-centric network structure called RCube, which is energy efficient and can deploy a redundancy scheme to improve the availability of data centers. Moreover, RCube shares many good properties with BCube, a well known server-centric network structure, yet its network size can be adjusted more conveniently. We also present a routing algorithm to find paths in RCube and an algorithm to build multiple parallel paths between any pair of source and destination servers. In addition, we theoretically analyze the power efficiency of the network and availability of RCube under server failure. Our comprehensive simulations demonstrate that RCube provides higher availability and flexibility to make trade-off among many factors, such as power consumption and aggregate throughput, than BCube, while delivering similar performance to BCube in many critical metrics, such as average path length, path distribution and graceful degradation, which makes RCube a very promising empirical structure for an enterprise data center network product.

关键词： Data center networks diameter parallel paths server-centric power efficiency high availability

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Primitive Instantiation Based Fault Localization Circuitry for high performance FPGA Designs 21st

Primitive Instantiation Based Fault Localization Circuitry f...

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21st international symposium on VLSI Design and Test (VDAT)

作者： Palchaudhuri, Ayan Dhar, Anindya Sundar Indian Inst Technol Kharagpur Dept Elect & Elect Commun Engn Kharagpur 721302 W Bengal India

ISBN: (纸本)9789811074707;9789811074691

The ever increasing demand to push the envelope for achieving superlative metrics of VLSI circuit performance along with denser logic packing and miniaturization of device dimensions, has rendered FPGAs to be more vulnerable to reliability hazards. This has led to reducing of the reliability and lifetime of VLSI chips. In this paper, we have proposed certain circuit techniques which comes along with the original design, to detect the presence of faulty FPGA logic slices, without significant compromise in performance. Primitive instantiation and constrained placement based approach was adopted for the circuit realizations to facilitate tracing of the exact faulty location, so that the faulty zones may be conveniently bypassed for fault-free circuit operation.

关键词： Carry chain Look-Up Table Fault localization FPGA Primitive instantiation

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Improving the querying efficiency of the PLWAH Bitmap algorithm 17

Improving the querying efficiency of the PLWAH Bitmap algori...

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21st international Database Engineering and Applications symposium, IDEAS 2017

作者： Taufen, Benjamin Sawin, Jason Chiu, David Computer and Information Sciences University of St. Thomas St. PaulMN United States Mathematics and Computer Science University of Puget Sound TacomaWA United States

ISBN: (纸本)9781450352208

Bitmap indices are commonly used for accessing large, read-only data. A bitmap is a simplified model of the underlying data in secondary storage. Its coarse representation enables the use of fast CPU operations to answer common database queries. Additionally, bitmaps are very compressible. Several known compression algorithms allow the compressed form of the bitmap to be queried directly, and one of which is Position List Word-Aligned Hybrid (PLWAH). PLWAH is modified hybrid run-length encoding scheme that can achieve better compression than traditional schemes such as Word-Aligned Hybrid (WAH). This improved compression introduces an increased query processing cost, of which we address in this paper. We present a technique that uses metadata to allow PLWAH's query algorithm to exploit logical short-circuiting opportunities, reducing the cost of certain queries. In our empirical study, we found that our approach achieved an average speedup of 1.41X over PLWAH for real scientific data sets. For specific queries, our approach realized speedups as high as 8000X. © 2017 Association for computing Machinery.

关键词： Metadata

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Energy-Efficient VLSI architecture & Implementation of Bi-modal Multi-banked Register-File Organization 21st

Energy-Efficient VLSI Architecture & Implementation of Bi-mo...

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21st international symposium on VLSI Design and Test (VDAT)

作者： Gudaparthi, Sumanth Shrestha, Rahul Int Inst Informat Technol IIIT Hyderabad Ctr VLSI & Embedded Syst Technol Hyderabad 500032 India Indian Inst Technol IIT Mandi Sch Comp & Elect Engn Mandi 175005 Himachal Prades India

ISBN: (纸本)9789811074707;9789811074691

For the execution of high-end applications of present-day scenario, processor consumes profound energy and its significant fraction is due to intensive register-file access in the processor architecture. Such fraction of energy required by the processor defers to reduce with the advancement of semiconductor technology and thereby, it is essential to design energy-efficient register-file architecture for the contemporary scenario. This paper presents new register-file architecture called the bi-modal multi-banked register-file organization to capture short term reused and short lived operands to alleviate load on register file to read and write. Additionally, instruction decode stage of the processor architecture is restructured to capture the reused and short lived register operands. On incorporating these new features, we have conceived a processor architecture that has been synthesized and post-layout simulated in 180nm complementary metal-oxide semiconductor (CMOS) technology node. It consumes 35 mW of total power at 200 MHz of clock frequency. The bi-modal multi-banked register-file organization stores a fraction of data bandwidth, which is local to the functional units, resulting in the reduction of cost for supplying data to the execute stage. Subsequently, the proposed architecture is made to execute MiBench benchmark kernels and it showed up to 55% improvement in energy saving over an embedded reduced instruction-set computer (RISC) processor architecture.

关键词： Register files computer architecture Embedded processor Energy conservation CMOS and very-large scale-integration (VLSI) design

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