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检索条件"任意字段=21st International Symposium on Computer Architecture and High Performance Computing"

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Design and Implementation of Mixed Parallel and Dataflow architecture for Intra-prediction Hardware in HEVC Decoder 21st

Design and Implementation of Mixed Parallel and Dataflow Arc...

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21st international symposium on VLSI Design and Test (VDAT)

作者： Choudhury, Rituparna Rangababu, P. Natl Inst Technol Meghalaya Dept Elect & Commun Engn Bijni Complex Shillong 793003 Meghalaya India

ISBN: (纸本)9789811074707;9789811074691

The objective of the paper is to implement an area efficient hardware for intra prediction in high efficiency video coding (HEVC) decoder for DC, angular and planar modes of all block sizes. viz., 64 x 64, 32 x 32, 16 x 16, 8 x 8 and 4 x 4. The proposed hardware is written in Verilog and implemented in field programmable gate array (FPGA) Virtex-7. The clock cycles consumed by the proposed design is the lowest as compared to the existing designs [7] as in the proposed architecture all the three modes ( DC, angular and planar modes) are executed in parallel. The reference pixels are processed and one 4 x 4 block is obtained at the output in one clock cycle as the architecture is designed to process 16 pixels (one 4 x 4 block) in parallel for all the three modes. Once the prediction for one mode of a block is completed the resources are released and made available to be used by next mode or next block. Thus the resource consumption is less as compared to existing designs where all the modes for each block is executed irrespective of encoder information which results in unnecessary resource usage.

关键词： high efficiency video coding (HEVC) Intra prediction Field programmable gate array (FPGA)

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Analysis using spectral clustering to predict internet gaming behaviours 17

Analysis using spectral clustering to predict internet gamin...

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21st international Database Engineering and Applications symposium, IDEAS 2017

作者： Rupert, Maya Samaha Hawi, Nazir S. Department of Computer Science Notre Dame University-Louaize Lebanon

ISBN: (纸本)9781450352208

As computers are becoming more powerful and with the availability of sophisticated data visualization software, the capability to extract knowledge from data for the benefit of individuals and society is imperative. Contemporary research barely started to reap the power of data science techniques to process and analyze data, and communicate results. Actually, research studies from various disciplines have been relying heavily on traditional statistical methods such as correlations and regressions. In this study, we propose a novel approach using clustering analysis to tackle the problem of the impact of Internet gaming. The special interest in Internet gaming is intensifying as it is spreading widely among students and as it is believed to have detrimental effects on their academic performance and sleep habits. We aim to identify patterns related to Internet gamers by using spectral clustering to determine the structure among Internet gaming, academic achievement, and sleep habits. Results show three distinctive clusters and a strong associations between Internet gaming disorder on one hand, and decline in both sleep hours and academic performance on the other hand. © 2017 Association for computing Machinery.

关键词： Cluster analysis

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Lightweight encryption algorithm based on modified XTEA for low-resource embedded devices 17

Lightweight encryption algorithm based on modified XTEA for ...

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21st international Database Engineering and Applications symposium, IDEAS 2017

作者： Kotel, Sonia Zeghid, Medien Machhout, Mohsen Tourki, Rached Higher Institute of Computer Science Communication Techniques of Hammam Sousse Sousse University Tunisia Laboratory of Electronics and Microelectronics Faculty of Sciences Monastir University Tunisia

ISBN: (纸本)9781450352208

The number of resource-limited wireless devices utilized in many areas of Internet of Things is growing rapidly;there is a concern about privacy and security. Various lightweight block ciphers are proposed;this work presents a modified lightweight block cipher algorithm. A Linear Feedback Shift Register is used to replace the key generation function in the XTEA1 Algorithm. Using the same evaluation conditions, we analyzed the software implementation of the modified XTEA using FELICS (Fair Evaluation of Lightweight Cryptographic Systems) a benchmarking framework which calculates RAM footprint, ROM occupation and execution time on three largely used embedded devices: 8-bit AVR microcontroller, 16-bit MSP microcontroller and 32-bit ARM microcontroller. Implementation results show that it provides less software requirements compared to original XTEA. We enhanced the security level and the software performance. © 2017 Association for computing Machinery.

关键词： Microcontrollers

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A high Speed KECCAK Coprocessor for Partitioned NSP architecture on FPGA Platform 21st

A High Speed KECCAK Coprocessor for Partitioned NSP Architec...

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21st international symposium on VLSI Design and Test (VDAT)

作者： Paul, Rourab Shukla, Sandeep Kumar Indian Inst Technol Dept Comp Sci & Engn Kanpur Uttar Pradesh India

ISBN: (纸本)9789811074707;9789811074691

The messages in the latest security protocols such as IPSec, TLS and SSL must be handled by high-speed crypto systems. Current computationally extensive cryptographic implementations on different platforms such as software, Application Specific Integrated Circuit (ASIC) and Field Programmable Gate Array (FPGA) without adequate optimization achieve lesser throughput than should be possible. In the paper we consider a cryptographic hashing algorithm KECCAK and its implementations. To achieve better throughput, the proposed implementations of KECCAK explores FPGA design spaces. In this paper three different architectures for KECCAK coprocessor are implemented in Artix-7 (XC7A100T, CSG324) FPGA platform. The Processing Element (PE) handles all communication interfaces, data paths and control signals hazards of Network Security Processor (NSP). A partitioned area in the system ensures that the processor data path is completely isolated from secret key memory. The memory to KECCAK core communication is done by Direct Memory Access Controller (DMA). The performances of the implemented KECCAK are better in terms of throughput and resource usage than the existing work reported in the literature.

关键词： KECCAK NSP DMA TLS/SSL FPGA high speed

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21st international Conference on Theory and Practice of Digital Libraries, TPDL 2017

21st International Conference on Theory and Practice of Digi...

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21st international Conference on Theory and Practice of Digital Libraries, TPDL 2017

ISBN: (纸本)9783319670072

The proceedings contain 63 papers. The special focus in this conference is on Theory and Practice of Digital Libraries. The topics include: Exploiting interlinked research metadata;preserving bibliographic relationships in mappings from FRBR to BIBFRAME 2.0;exploring ontology-enhanced bibliography databases using faceted search;taxonomic corpus-based concept summary generation for document annotation;a german corpus for a historical epidemic with temporal annotation;facet embeddings for explorative analytics in digital libraries;automatic hierarchical categorization of research expertise using minimum information;extracting event-centric document collections from large-scale web archives;information governance maturity model final development iteration;challenges of research data management for high performance computing;how linked data can aid machine learning-based tasks;classifying document types to enhance search and recommendations in digital libraries;understanding the influence of hyperparameters on text embeddings for text classification tasks;what users search for and why;on the uses of word sense change for research in the digital humanities;multi-aspect entity-centric analysis of big social media archives;a comparative study of language modeling to instance-based methods, and feature combinations for authorship attribution;semantic author name disambiguation with word embeddings;towards a knowledge graph representing research findings by semantifying survey articles;integration of scholarly communication metadata using knowledge graphs;analysing scholarly communication metadata of computer science events;high-pass text filtering for citation matching and sentiment classification over opinionated data streams through informed model adaptation.

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Effectiveness of high Permittivity Spacer for Underlap Regions of Wavy-Junctionless FinFET at 22 nm Node and Scaling Short Channel Effects 21st

Effectiveness of High Permittivity Spacer for Underlap Regio...

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21st international symposium on VLSI Design and Test (VDAT)

作者： Vandana, B. Das, J. K. Mohapatra, S. K. Kaushik, B. K. KIIT Univ Sch Elect Engn Bhubaneswar India Indian Inst Technol Roorkee Dept Elect & Commun Engn Roorkee Uttar Pradesh India

ISBN: (纸本)9789811074707;9789811074691

In this work, an attempt has been made to investigate the performance of a new device, Wavy Junctionless FinFET at 22 nm node using low to high permittivity spacer for underlap regions. An alternative V-TH extraction method has been demonstrated, which signifies the importance of cannel length at the nanoscale regime. The device layer Silicon film possesses uniform doping profile, where the current is controlled by channel doping and the mobility of charge carriers which account the bulk conduction instead of surface conduction. Due to the scalability of device dimensions, underlap regions are preferred to differentiate the control and the location of dopant atoms along the conduction region and hence this enhances the device performances. The simulation results enlighten the effectiveness of high permittivity of spacer region through performance evaluation. The simulated results exhibit an SS of 64 mV/decade, DIBL of 26 mV/V and I-ON/I-OFF ratio of 10(7).

关键词： Wavy-JL FinFET Nanowire Silicon on insulator (SOI) FinFET high-kappa spacer Short channel parameters V-TH extraction method

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Comparison of dynamic itemset mining algorithms for multiple support thresholds 17

Comparison of dynamic itemset mining algorithms for multiple...

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21st international Database Engineering and Applications symposium, IDEAS 2017

作者： Abuzayed, Nourhan N. Ergenç, Belgin Department of Computer Engineering Izmir Institute of Technology Izmir Turkey

ISBN: (纸本)9781450352208

Mining1 frequent itemsets is an important part of association rule mining process. Handling dynamic aspect of databases and multiple support threshold requirements of items are two important challenges of frequent itemset mining algorithms. Most of the existing dynamic itemset mining algorithms are devised for single support threshold whereas multiple support threshold algorithms are static. This work focuses on dynamic update problem of frequent itemsets under multiple support thresholds and proposes tree-based Dynamic CFP-Growth++ algorithm. Proposed algorithm is compared to our previous dynamic algorithm Dynamic MIS [50] and a recent static algorithm CFP-Growth++ [2] and, findings are;in dynamic database, 1) both of the dynamic algorithms are better than the static algorithm CFP-Growth++, 2) as memory usage performance;Dynamic CFP-Growth++ performs better than Dynamic MIS, 3) as execution time performance;Dynamic MIS is better than Dynamic CFP-Growth++. In short, Dynamic CFP-Growth++ and Dynamic MIS have a trade-off relationship in terms of memory usage and execution time. © 2017 Association for computing Machinery.

关键词： Association rules

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performance Optimized 64b/66b Line Encoding Technique for high Speed SERDES Devices 21st

Performance Optimized 64b/66b Line Encoding Technique for Hi...

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21st international symposium on VLSI Design and Test (VDAT)

作者： Singh, Jatindeep Mohapatra, Satyajit Mohapatra, Nihar Ranjan Indian Inst Technol Dept Elect Engn Gandhinagar 382355 India

ISBN: (纸本)9789811074707;9789811074691

The 64b/66b technique conventionally is suited for low BER fiber optic channels, but can be extended for higher BER channels by including proper error correcting code and preamble. A modified 64b/66b line encoding technique for the design of high speed SERDES is proposed. Unlike earlier 8b/10b technology, run-length is no more guaranteed but is statistically bound. Generated polynomials are statistically tested in MATLAB prior VHDL implementation. Optimal selection of primitive polynomial limits run length to 11 and provides sub-optimal data security. Proposed 64/66b encoding technique reduces overhead by 15.8% (at 6.3% CRC) with respect to conventional 8b/10b, while is also suited for high BER channels like wireless and free space. A performance optimum between security, run-length, ISI and DC equalization, this scheme finds potential application in space camera electronics, 5G technology and other IOT applications like driverless cars that require to handle large volumes of real time data with sufficient security on high BER wireless channels.

关键词： Serializer-Deserializer (SERDES) Inter-Symbol Interference (ISI) Cyclic redundancy check (CRC) Encoding technique Bit error rate (BER)

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Exploring deletion strategies for the BoND-tree in multidimensional non-ordered discrete data spaces 17

Exploring deletion strategies for the BoND-tree in multidime...

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21st international Database Engineering and Applications symposium, IDEAS 2017

作者： Cherniak, Ramblin Zhu, Qiang Gu, Yarong Pramanik, Sakti Department of Computer and Information Science University of Michigan - Dearborn DearbornMI48128 United States Department of Computer Science and Engineering Michigan State University East LansingMI48824 United States

ISBN: (纸本)9781450352208

Box queries on a dataset in a multidimensional data space are a type of query which specifies a set of allowed values for each dimension. Indexing a dataset in a multidimensional Non-ordered Discrete Data Space (NDDS) for supporting efficient box queries is becoming increasingly important in many application domains such as genome sequence analysis. The BoND-tree was recently introduced as an index structure specifically designed for box queries in an NDDS. Earlier work focused on developing strategies for building an effective BoND-tree to achieve high query performance. Developing efficient and effective techniques for deleting indexed vectors from the BoND-tree remains an open issue. In this paper, we present three deletion algorithms based on different underflow handling strategies in an NDDS. Our study shows that incorporating a new BoND-tree inspired heuristic can provide improved performance compared to the traditional underflow handling heuristics in NDDSs. © 2017 Copyright held by the owner/author(s).

关键词： Genes

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2015 IEEE 21st international symposium on high performance computer architecture, HPCA 2015

2015 IEEE 21st International Symposium on High Performance C...

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2015 21st IEEE international symposium on high performance computer architecture, HPCA 2015

ISBN: (纸本)9781479989300

The proceedings contain 55 papers. The topics discussed include: exploring architectural heterogeneity in intelligent vision systems;increasing multicore system efficiency through intelligent bandwidth shifting;exploiting compressed block size as an indicator of future reuse;talus: a simple way to remove cliffs in cache performance;priority-based cache allocation for throughput processors;bamboo ECC: strong, safe, and flexible codes for reliable computer memory;heterogeneous memory architectures: a HW/SW approach for mixing die-stacked and off-package memories;domain knowledge based energy management in handhelds;GPU voltage noise: characterization and hierarchical smoothing of spatial and temporal voltage noise interference in GPU architectures;and hierarchical private/shared classification: the key to simple and efficient coherence for clustered cache hierarchies.

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