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检索条件"任意字段=21st International Symposium on Computer Architecture and High Performance Computing"

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Understanding GPU Errors on Large-scale HPC Systems and the Implications for System Design and Operation 21

Understanding GPU Errors on Large-scale HPC Systems and the ...

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IEEE 21st international symposium on high performance computer architecture (HPA)

作者： Tiwari, Devesh Gupta, Saurabh Rogers, James Maxwell, Don Rech, Paolo Vazhkudai, Sudharshan Oliveira, Daniel Londo, Dave DeBardeleben, Nathan Navaux, Philippe Carro, Luigi Bland, Arthur Cray Inc Seattle WA USA Los Alamos Natl Lab Los Alamos NM USA Univ Fed Rio Grande do Sul BR-90046900 Porto Alegre RS Brazil Oak Ridge Natl Lab Oak Ridge Leadership Comp Facil Oak Ridge TN 37831 USA

ISBN: (纸本)9781479989300

Increase in graphics hardware performance and improvements in programmability has enabled GPUs to evolve from a graphics-specific accelerator to a general-purpose computing device. Titan, the world's second fastest supercomputer for open science in 2014, consists of more than 18,000 GPUs that scientists from various domains such as astrophysics, fusion, climate, and combustion use routinely to run large-scale simulations. Unfortunately, while the performance efficiency of GPUs is well understood, their resilience characteristics in a large-scale computing system have not been fully evaluated. We present a detailed study to provide a thorough understanding of GPU errors on a large-scale GPU-enabled system. Our data was collected from the Titan supercomputer at the Oak Ridge Leadership computing Facility and a GPU cluster at the Los Alamos National Laboratory. We also present results from our extensive neutron-beam tests, conducted at Los Alamos Neutron Science Center (LANSCE) and at ISIS (Rutherford Appleton Laboratories, UK), to measure the resilience of different generations of GPUs. We present several findings from our field data and neutron-beam experiments, and discuss the implications of our results for future GPU architects, current and future HPC computing facilities, and researchers focusing on GPU resilience.

关键词： GRAPPER PICK UP Graphics Processing Unit Resilience Los Alamos National Laboratory high performance computing programmability supercomputer graphic images Titan

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Value Reuse Potential in ARM architectures

Value Reuse Potential in ARM Architectures

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international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Rodrigo C. De Moura Giovane O. Torres Maurício L. Pilla Laércio L. Pilla Amarildo T. Da Costa Felipe M.G. França PPGC - UFPEL St. Pelotas Brazil Department of Informatics and Statistics - UFSC Florianópolis Brazil IME Rio de Janeiro Brazil COPPE - UFRJ Rio de Janeiro Brazil

Code execution in modern superscalar processors is inherently redundant. Many instructions execute repeatedly with the same inputs, producing the same outputs, thus wasting resources in the process. Value reuse techniques memorize previous executions of instructions, blocks or traces which may be reused if they appear again with the same input contexts. Although trace reuse techniques show great potential for both performance and energy consumption improvement, they have not been studied yet in one of the most widely available computer architectures - the ARM architecture. In this paper, the main issues with reusing traces in instruction sets with conditional execution are revisited. Afterwards, the reuse potential in the benchmark suite MiBench is analyzed varying (i) how traces are generated, and (ii) the size of reuse tables. Our results show that a memorization table of 32 KiB allows to reuse 18.36% of the total instructions on average.

关键词： computer architecture Registers Context Pipelines Instruction sets computers

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A novel PUF based on cell error rate distribution of stT-RAM 21

A novel PUF based on cell error rate distribution of STT-RAM

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21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016

作者： Zhang, Xian Guangyu, Sun Zhang, Yaojun Chen, Yiran Li, Hai Wen, Wujie Di, Jia Center for Energy-Efficient Computing and Applications Peking University Beijing100871 China Collaborative Innovation Center of High Performance Computing NUDT Changsha410073 China Department of Electrical and Computer Engineering University of Pittsburgh PittsburghPA15261 United States Department of Electrical and Computer Engineering Florida International University MiamiFL33199 United States Computer Science and Computer Engineering University of Arkansas FayettevilleAR72701 United States

ISBN: (纸本)9781467395694

Physical Unclonable Functions (PUFs) have been widely proposed as security primitives to provide device identification and authentication. Recently, PUFs based on Non-volatile Memory (NVM) are widely proposed since the promise of NVMs' wide application. In addition, NVM-based PUFs are considered to be more immune to invasive attack and simulation attack than CMOS-based PUFs. However, the existing NVM-based PUF either shows the unreliability under environmental variations or need extra modifications to the IC manufacturing process. In this work, we propose err-PUF, a novel PUF design based on the cell error rate distribution of stT-RAM. Instead of using the distribution directly, we generate a stable fingerprint based on a novel concept called Error-rate Differential Pair (EDP) without modifications to the read/write circuits. Comprehensive results demonstrate that err-PUF can achieve sufficient reliability under environmental variations, which can significantly impact the cell error rates. Moreover, compared with existing approaches, err-PUF has a higher speed and lower power consumption with negligible overhead. © 2016 IEEE.

关键词： Hardware security

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Effective user relevance feedback for image retrieval with image signatures 16

Effective user relevance feedback for image retrieval with i...

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21st Australasian Document computing symposium, ADCS 2016

作者： Uluwitige, Dinesha Chathurani Nanayakkara Wasam Geva, Shlomo Zuccon, Guido Chandran, Vinod Chappell, Timothy School of Electrical Engineering and Computer Science Queensland University of Technology BrisbaneQLD Australia

ISBN: (纸本)9781450348652

Content-based image retrieval (CBIR) has attracted much attention due to the exponential growth of digital image collections that have become available in recent years. Relevance feedback (RF) in the context of search engines is a query expansion technique, which is based on relevance judgments about the top results that are initially returned for a given query. RF can be obtained directly from end users, inferred indirectly from user interactions with a result list, or even assumed (aka pseudo relevance feedback). RF information is used to generate a new query, aiming to re-focus the query towards more relevant results. This paper presents a methodology for use of signature based image retrieval with a user in the loop to improve retrieval performance. The significance of this study is twofold. First, it shows how to effectively use explicit RF with signature based image retrieval to improve retrieval quality and eficiency. Second, this approach provides a mechanism for end users to refine their image queries. This is an important contribution because, to date, there is no effective way to reformulate an image query;our approach provides a solution to this problem. Empirical experiments have been carried out to study the behaviour and optimal parameter settings of this approach. Empirical evaluations based on standard benchmarks demonstrate the effectiveness of the proposed approach in improving the performance of CBIR in terms of recall, precision, speed and scalability. © 2016 ACM.

关键词： Search engines

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An I/O-efficient buffer batch replacement policy for update-intensive graph databases 21st

An I/O-efficient buffer batch replacement policy for update-...

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21st international Conference on Database Systems for Advanced Applications, DASFAA 2016

作者： Zhou, Ningnan Zhou, Xuan Zhang, Xiao Wang, Shan Liu, Ling MOE Key Laboratory of DEKE Renmin University of China Beijing China School of Information Renmin University of China Beijing100872 China College of Computing Georgia Institute of Technology Atlanta China

ISBN: (纸本)9783319320489

With the proliferation of graph based applications, such as social network management and Web structure mining, update-intensive graph databases have become an important component of today’s data management platforms. Several techniques have been recently proposed to exploit locality on both data organization and computational model in graph databases. However, little investigation has been conducted on buffer management of graph databases. To the best of our knowledge, current buffer managers of graph databases suffer performance loss caused by unnecessary random I/O access. To solve this problem, we develop a novel batch replacement policy for buffer management. This policy enables us to maximally exploit sequential I/O to improve the performance of graph database. To enable the policy, we devise a segment tree based buffer manager to efficiently maintains optimal replacement plan. Extensive experiments on real-world and synthetic datasets demonstrate the superiority of our method. © Springer international Publishing Switzerland 2016.

关键词： Graph Databases

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SNNAP: Approximate computing on Programmable SoCs via Neural Acceleration 21

SNNAP: Approximate Computing on Programmable SoCs via Neural...

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IEEE 21st international symposium on high performance computer architecture (HPA)

作者： Moreau, Thierry Wyse, Mark Nelson, Jacob Sampson, Adrian Esmaeilzadeh, Hadi Ceze, Luis Oskin, Mark Univ Washington Seattle WA 98195 USA Georgia Inst Technol Atlanta GA 30332 USA

ISBN: (纸本)9781479989300

Many applications that can take advantage of accelerators are amenable to approximate execution. Past work has shown that neural acceleration is a viable way to accelerate approximate code. In light of the growing availability of on-chip field-programmable gate arrays (FPGAs), this paper explores neural acceleration on off-the-shelf programmable SoCs. We describe the design and implementation of SNNAP, a flexible FPGA-based neural accelerator for approximate programs. SNNAP is designed to work with a compiler workflow that configures the neural network's topology and weights instead of the programmable logic of the FPGA itself. This approach enables effective use of neural acceleration in commercially available devices and accelerates different applications without costly FPGA reconfigurations. No hardware expertise is required to accelerate software with SNNAP, so the effort required can be substantially lower than custom hardware design for an FPGA fabric and possibly even lower than current "C-to-gates" high-level synthesis (HLS) tools. Our measurements on a Xilinx Zynq FPGA show that SNNAP yields a geometric mean of 3.8xspeedup (as high as 38.1x) and 2.8x energy savings (as high as 28x) with less than 10% quality loss across all applications but one. We also compare SNNAP with designs generated by commercial HLS tools and show that SNNAP has similar performance overall, with better resource-normalized throughput on 4 out of 7 benchmarks.

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On the performance of a dual-hop network with a mobile relay in a Nakagami fading environment

On the performance of a dual-hop network with a mobile relay...

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IEEE international Workshop on computer-Aided Modeling, Analysis, and Design of Communication Links and Networks, CAMAD

作者： Constantine Mukasa Valentine A. Aalo George Efthymoglou Department of Computer & Electrical Engineering and Computer Science Florida Atlantic University Boca Raton FL USA University of Pireaus Piraeus GR

ISBN: (纸本)9781509025596

high speed trains are becoming a popular means of transportation all over the world, such that it is necessary to develop and deploy an infrastructure to provide broadband to passengers on the train. However, there are several challenges to high speed communication systems including the fact that channel conditions change drastically hindering channel estimation accuracy and overall system performance, which leads to link failure. Cooperative relaying is one of the novel schemes used in wireless communication to improve throughput and system performance. In this paper, we propose a general analytical approach to evaluate the performance of a dual-hop network with a fixed relay on a train carriage in a Nakagami-m fading environment. The relay is assumed to employ either decode-and-forward (DF) or amplify-and-forward (AF) relaying scheme. Both, the relay and destination nodes are assumed to be mobile and follow the Random direction (RD) mobility model. Under this setting, we derive exact expressions for outage probability and average bit error probability (ABEP). The derived analytical results are general and applicable to several network topology dimensions, fading conditions, and digital modulation schemes. The analytical results are verified by Monte Carlo simulations.

关键词： Relays Fading channels Mobile communication Mobile computing Signal to noise ratio Protocols Network topology

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Bamboo ECC: strong, Safe, and Flexible Codes for Reliable computer Memory 21

Bamboo ECC: Strong, Safe, and Flexible Codes for Reliable Co...

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IEEE 21st international symposium on high performance computer architecture (HPA)

作者： Kim, Jungrae Sullivan, Michael Erez, Mattan Univ Texas Austin Dept Elect & Comp Engn Austin TX 78712 USA

ISBN: (纸本)9781479989300

Growing computer system sizes and levels of integration have made memory reliability a primary concern, necessitating strong memory error protection. As such, large-scale systems typically employ error checking and correcting codes to trade redundant storage and bandwidth for increased reliability. While stronger memory protection will be needed to meet reliability targets in the future, it is undesirable to further increase the amount of storage and bandwidth spent on redundancy. We propose a novel family of single-tier ECC mechanisms called Bamboo ECC to simultaneously address the conflicting requirements of increasing reliability while maintaining or decreasing error protection overheads. Relative to the state-of-the-art single-tier error protection, Bamboo ECC codes have superior correction capabilities, all but eliminate the risk of silent data corruption, and can also increase redundancy at a fine granularity, enabling more adaptive graceful downgrade schemes. These strength, safety, and flexibility advantages translate to a significantly more reliable memory system. To demonstrate this, we evaluate a family of Bamboo ECC organizations in the context of conventional 72b and 144b DRAM channels and show the significant error coverage and memory lifespan improvements of Bamboo ECC relative to existing SEC-DED, chipkill-correct and double-chipkill-correct schemes.

关键词： Error correction codes Elliptic curve cryptography EMERGENCY CONTROL CENTERS computer memory data corruption error protection redundancy bamboos Bandwidth error checking store protection Fine Grain Size Cache Memory System one layer Codes

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Software Rejuvenation Schemes for Time Warp-based PDES 21

Software Rejuvenation Schemes for Time Warp-based PDES

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IEEE 21st Pacific Rim international symposium on Dependable computing (PRDC 2015)

作者： Fukumoto, Satoshi Ohara, Mamoru Tokyo Metropolitan Univ Fac Syst Design Hino Tokyo 1910065 Japan Tokyo Metropolitan Ind Technol Res Inst Koto Tokyo 1350064 Japan

ISBN: (纸本)9781467393768

Software rejuvenation is a technique to prevent the aging of running software. Recently, benefits of software rejuvenation in high-performance computing (HPC) areas have received attention. In time warp-based parallel discrete event simulation (PDES) systems, it is important to improve performance to equalize simulation progress in processes. In this article, we consider a number of schemes for time warp-based PDES to avoid the imbalance simulation progress introduced by rejuvenation.

关键词： software rejuvenation high-performance computing parallel discrete event simulation (PDES) time warp

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A position-based method for the extraction of financial information in PDF documents 16

A position-based method for the extraction of financial info...

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21st Australasian Document computing symposium, ADCS 2016

作者： Potvin, Benoit Villemaire, Roger Le, Ngoc-Tan Université du Québec à Montréal Department of Computer Science MontréalQCH3C 3P8 Canada

ISBN: (纸本)9781450348652

Financial documents are omnipresent and necessitate extensive human efforts in order to extract, validate and export their content. Considering the high importance of such data for effective business decisions, the need for accuracy goes beyond any attempt to accelerate the process or save resources. While many methods have been suggested in the literature, the problem to automatically extract reliable financial data remains difficult to solve in practice and even more challenging to implement in a real life context. This difficulty is driven by the specific nature of financial text where relevant information is principally contained in tables of varying formats. Table Extraction (TE) is considered as an essential but difficult step for restructuring data in a handleable format by identifying and decomposing table components. In this paper, we present a novel method for extracting financial information by the means of two simple heuristics. Our approach is based on the idea that the position of information, in unstructured but visually rich documents { as it is the case for the Portable Document Format (PDF) - is an indicator of semantic relatedness. This solution has been developed in partnership with the Caisse de Dépot et Placement du Québec. We present here our method and its evaluation on a corpus of 600 financial documents, where an F-measure of 91% is reached. © 2016 ACM.

关键词： Extraction

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