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检索条件"任意字段=21st International Symposium on Computer Architecture and High Performance Computing"

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Investigation of high-Level Synthesis tools' applicability to data acquisition systems design based on the CMS ECAL Data Concentrator Card example 21

Investigation of High-Level Synthesis tools' applicability t...

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21st international Conference on computing in high Energy and Nuclear Physics (CHEP)

作者： Husejko, Michal Evans, John Rasteiro Da Silva, Jose Carlos CERN European Lab Nucl Res CH-1211 Geneva 23 Switzerland Lab Instrumentacao & Fis Expt Particulas LIP Oporto Portugal

high-Level Synthesis (HLS) for Field-Programmable Logic Array (FPGA) programming is becoming a practical alternative to well-established VHDL and Verilog languages. This paper describes a case study in the use of HLS tools to design FPGA-based data acquisition systems (DAQ). We will present the implementation of the CERN CMS detector ECAL Data Concentrator Card (DCC) functionality in HLS and lessons learned from using HLS design flow. The DCC functionality and a definition of the initial system-level performance requirements (latency, bandwidth, and throughput) will be presented. We will describe how its packet processing control centric algorithm was implemented with VHDL and Verilog languages. We will then show how the HLS flow could speed up design-space exploration by providing loose coupling between functions interface design and functions algorithm implementation. We conclude with results of real-life hardware tests performed with the HLS flow-generated design with a DCC Tester system.

关键词： computer hardware description languages

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performance Evaluation of the ATLAS IBL Calibration 21

Performance Evaluation of the ATLAS IBL Calibration

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21st international Conference on computing in high Energy and Nuclear Physics (CHEP)

作者： Kretz, M. Heidelberg Univ ZITI Inst Tech Informat Mannheim Germany

The Insertable-B-Layer (IBL) has recently been commissioned at the ATLAS Experiment, adding 12 million channels to the existing Pixel Detector. The front-end chips (FE-14) are connected to newly designed readout hardware situated in a VME crate. In order to take data under uniform conditions, one needs to periodically tune the detector in short breaks between data-taking sessions to accommodate for radiation damage and aging effects. Tuning involves a variety of components, ranging from high-level steering and analysis software (PixLib) running on commodity hardware, to embedded components situated inside the VME crate that feature only a minimal or no operating system at all. Understanding the interactions between these components is key in debugging and optimizing the tuning procedures to become more efficient. We therefore implement an instrumentation framework aimed at all major components. It features a uniform interface to the user and is able to take instrumentation data with his precision. A central server application is used to gather the instrumentation data of a tuning session. It processes the data and saves it into an SQLite database for later analysis.

关键词： computer hardware

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Running ATLAS workloads within massively parallel distributed applications using Athena Multi-Process framework (AthenaMP) 21

Running ATLAS workloads within massively parallel distribute...

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21st international Conference on computing in high Energy and Nuclear Physics (CHEP)

作者： Calafiura, Paolo Leggett, Charles Seuster, Rolf Tsulaia, Vakhtang Van Gemmeren, Peter Univ Calif Berkeley Lawrence Berkeley Natl Lab 1 Cyclotron Rd Berkeley CA 94720 USA TRIUMF Vancouver BC V6T 2A3 Canada Argonne Natl Lab Argonne IL 60439 USA

AthenaMP is a multi-process version of the ATLAS reconstruction, simulation and data analysis framework Athena. By leveraging Linux fork and copy-on-write mechanisms, it allows for sharing of memory pages between event processors running on the same compute node with little to no change in the application code. Originally targeted to optimize the memory footprint of reconstruction jobs, AthenaMP has demonstrated that it can reduce the memory usage of certain configurations of ATLAS production jobs by a factor of 2. AthenaMP has also evolved to become the parallel event-processing core of the recently developed ATLAS infrastructure for fine-grained event processing (Event Service) which allows the running of AthenaMP inside massively parallel distributed applications on hundreds of compute nodes simultaneously. We present the architecture of AthenaMP, various strategies implemented by AthenaMP for scheduling workload to worker processes (for example: Shared Event Queue and Shared Distributor of Event Tokens) and the usage of AthenaMP in the diversity of ATLAS event processing workloads on various computing resources: Grid, opportunistic resources and HPC.

关键词： computer operating systems

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FiNS: A Framework for Accelerating Nested Simulations on Heterogeneous Platforms

FiNS: A Framework for Accelerating Nested Simulations on Het...

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21st international Conference on Parallel and Distributed computing (Euro-Par)

作者： Cramwinckel, Joris Singor, stefan Varbanescu, Ana Lucia Ortec Finance Rotterdam Netherlands Delft Univ Technol Delft Netherlands Univ Amsterdam Amsterdam Netherlands

ISBN: (纸本)9783319273082;9783319273075

Insurers use advanced risk management models to, among other things, compute required capital for different sources of financial risks. In these models the application of nested simulations becomes increasingly important. To keep computation times within acceptable limits high-performance computing is required. In this work we present a framework designed to significantly improve the performance of nested simulations by using heterogeneous computing. Specifically, we use modern features from CUDA - streams, Hyper-Q, and Multi-Process Service to take full advantage of the massive parallelism of modern GPUs. We manage to reduce the execution time of such simulations from several hours to tens of minutes.

关键词： CPU-GPU heterogeneous computing Asset & Liability Management Nested simulations CUDA streams CUDA Hyper-Q

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Towards Application Variability Handling with Component Models: 3D-FFT Use Case study

Towards Application Variability Handling with Component Mode...

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21st international Conference on Parallel and Distributed computing (Euro-Par)

作者： Lanore, Vincent Perez, Christian Richard, Jerome Ecole Normale Super Lyon F-69364 Lyon France Inria Avalon Res Team LIP Lyon France

ISBN: (纸本)9783319273082;9783319273075

To harness the computing power of supercomputers, HPC application algorithms have to be adapted to the underlying hardware. This is a costly and complex process which requires handling many algorithm variants. This paper studies the ability of the component model (LC)-C-2 to express and handle the variability of HPC applications. The goal is to ease application adaptation. Analysis and experiments are done on a 3D-FFT use case. Results show that (LC)-C-2, and components in general, offer a generic and simple handling of 3D-FFT variants while obtaining performance close to well-known libraries.

关键词： Application adaptation Component models high-performance computing

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BRAINIAC: Bringing reliable accuracy into neurally-implemented approximate computing

BRAINIAC: Bringing reliable accuracy into neurally-implement...

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IEEE symposium on high-performance computer architecture

作者： Beayna Grigorian Nazanin Farahpour Glenn Reinman Computer Science Department University of California

Applications with large amounts of data, real-time constraints, ultra-low power requirements, and heavy computational complexity present significant challenges for modern computing systems, and often fall within the category of high performance computing (HPC). As such, computer architects have looked to high performance single instruction multiple data (SIMD) architectures, such as accelerator-rich platforms, for handling these workloads. However, since the results of these applications do not always require exact precision, approximate computing may also be leveraged. In this work, we introduce BRAINIAC, a heterogeneous platform that combines precise accelerators with neural-network-based approximate accelerators. These reconfigurable accelerators are leveraged in a multi-stage flow that begins with simple approximations and resorts to more complex ones as needed. We employ high-level, application-specific light-weight checks (LWCs) to throttle this multi-stage acceleration flow and reliably ensure user-specified accuracy at runtime. Evaluation of the performance and energy of our heterogeneous platform for error tolerance thresholds of 5%-25% demonstrates an average of 3× gain over computation that only includes precise acceleration, and 15×-35× gain over software-based computation.

关键词： Approximation methods Acceleration Artificial neural networks Hardware RNA Benchmark testing Software

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Design of a Hybrid Multicore Platform for high performance Reconfigurable computing 1

Design of a Hybrid Multicore Platform for High Performance R...

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1st Nordic Circuits Systems Conference (NORCAS) - NORCHIP / international symposium on System Chip (SoC) 2015

作者： Hussain, Waqar Hoffmann, Henry Ahonen, Tapani Nurmi, Jari Tampere Univ Technol Dept Elect & Commun Engn FI-33101 Tampere Finland Univ Chicago Dept Comp Sci Chicago IL 60637 USA

ISBN: (纸本)9781467365765

This paper presents a loosely-coupled, hybrid architecture of homogeneous and heterogeneous cores integrated together over a Network-on-Chip (NoC). The architecture efficiently utilizes the NoC bandwidth by keeping a balance between the instantiated number of computational and communication nodes. Furthermore, the architecture also provides a mixed flavor of homogeneous general-purpose processing and heterogeneous reconfigurable computing. Prior approaches have mostly considered homogeneous and heterogeneous platforms as two different design paradigms despite both show domain-specific performance advantages over each other. In this context, the proposed architecture is designed for nine NoC nodes, arranged in a topology of three rows and three columns. The middle row contains three homogeneous Reduced Instruction Set computer (RISC) cores and rest of the nodes are integrated with Coarse-Grain Reconfigurable Arrays (CGRAs) of application-specific sizes. The overall architecture is template-based which can be crafted to application's performance requirements. The NoC allows loose coupling, so all the cores can mutually exchange the data as well as enable independent and simultaneous execution. Contrarily, the user can program the middle layer of RISC cores for specific data/control dependencies among all the cores. The system mitigates power dissipation as the CGRAs are custom tailored for heterogeneous computing. The platform is evaluated for a proof-of-concept test comprising of massively-parallel signal processing algorithms. Synthesis results from a Field Programmable Gate Array device are used to establish comparisons and evaluation against some of the existing state-of-the-art multicore platforms in terms of multiple performance metrics.

关键词： core performance metrics configurability Core samples loose coupling Platform Building construction architecture composite structures Multi-core processors Ganglia middle surface course Heterogeneous Reduced instruction set computers RNA-Induced Silencing Complex

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performance of Tracking, b-tagging and Jet/MET reconstruction at the CMS high Level Trigger 21

Performance of Tracking, b-tagging and Jet/MET reconstructio...

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21st international Conference on computing in high Energy and Nuclear Physics (CHEP)

作者： Tosi, Mia Univ Padua Dipartimento Fis & Astron Via Marzolo 8 I-35131 Padua Pd Italy Ist Nazl Fis Nucl I-35131 Padua Pd Italy

The trigger systems of the LHC detectors play a crucial role in determining the physics capabilities of experiments. In 2015, the center-of-mass energy of proton-proton collisions will reach 13 TeV up to an unprecedented luminosity of 1 x 10(34) cm(-2)s(-1). A reduction of several orders of magnitude of the event rate is needed to reach values compatible with detector readout, offline storage and analysis capabilities. The CMS experiment has been designed with a two-level trigger system: the Level-1 Trigger (L1T), implemented on custom-designed electronics, and the high Level Trigger (HLT), a streamlined version of the offline reconstruction software running on a computer farm. A software trigger system requires a trade-off between the complexity of the algorithms, the sustainable output rate, and the selection efficiency. With the computing power available during the 2012 data taking the maximum reconstruction time at HLT was about 200 ms per event, at the nominal LIT rate of 100 kHz. Tracking algorithms are widely used in the HLT in the object reconstruction through particle-flow techniques as well as in the identification of b-jets and lepton isolation. Reconstructed tracks are also used to distinguish the primary vertex, which identifies the hard interaction process, from the pileup ones. This task is particularly important in the LHC environment given the large number of interactions per bunch crossing: on average 25 in 2012, and expected to be around 40 in Run II with a large contribution from out-of-time particles. In order to cope with tougher conditions the tracking and vertexing techniques used in 2012 have been largely improved in terms of timing and efficiency in order to keep the physics reach at the level of Run I conditions. We will present the performance of these newly developed algorithms, discussing their impact on the b-tagging performances as well as on the jet and missing transverse energy reconstruction.

关键词： Digital storage

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Teaching Heart Modeling and Simulation on Parallel computing Systems

Teaching Heart Modeling and Simulation on Parallel Computing...

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21st international Conference on Parallel and Distributed computing (Euro-Par)

作者： Sozykin, Andrey Chernoskutov, Mikhail Koshelev, Anton Zverev, Vladimir Ushenin, Konstantin Solovyova, Olga Inst Math & Mech UrB RAS Ekaterinburg Russia Ural Fed Univ Ekaterinburg Russia Inst Immunol & Physiol UrB RAS Ekaterinburg Russia

ISBN: (纸本)9783319273082;9783319273075

high performance computing (HPC) is an interdisciplinary field of study, which requires learning a number of topics, including not only parallel programming, but also numerical methods and domain science. stand-alone parallel computing courses are insufficient for thorough HPC education. We present an interdisciplinary track of coherent courses devoted to modeling and simulation of the heart on parallel computing systems for master students at the Ural Federal University. The track consists of three modules: parallel and distributed computing, heart modeling, and numerical methods. Knowledge of numerical methods and heart modeling provides the students with the ability to acquire profound parallel programming skills by working out on the comprehensive programming assignment and complex heart modeling projects. Interdisciplinary approach also increases students' motivation and involvement.

关键词： high performance computing Distributed computing HPC education Heart simulation Living system simulation

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Scalable communication architecture for network-attached accelerators

Scalable communication architecture for network-attached acc...

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IEEE symposium on high-performance computer architecture

作者： Sarah Neuwirth Dirk Frey Mondrian Nuessle Ulrich Bruening Institute of Computer Engineering University of Heidelberg Germany EXTOLL GmbH Germany

On the road to Exascale computing, novel communication architectures are required to overcome the limitations of host-centric accelerators. Typically, accelerator devices require a local host CPU to configure and operate them. This limits the number of accelerators per host system. Network-attached accelerators are a new architectural approach for scaling the number of accelerators and host CPUs independently. In this paper, the communication architecture for network-attached accelerators is described which enables remote initialization and control of the accelerator devices. Furthermore, an operative prototype implementation is presented. The prototype accelerator node consists of an Intel Xeon Phi coprocessor and an EXTOLL NIC. The EXTOLL interconnect provides new features to enable accelerator-to-accelerator direct communication without a local host. Workloads can be dynamically assigned to CPUs and accelerators at run-time in an N to M ratio. The latency, bandwidth, and performance of the low-level implementation and MPI communication layer are presented. The LAMMPS molecular dynamics simulator is used to evaluate the communication architecture. The internode communication time is improved by up to 47%.

关键词： computer architecture Microwave integrated circuits Ports (computers) Bismuth Acceleration Hardware Scalability

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