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检索条件"任意字段=21st International Symposium on Computer Architecture and High Performance Computing"

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Addressing the Last Roadblock for Message Logging in HPC: Alleviating the Memory Requirement Using Dedicated Resources

Addressing the Last Roadblock for Message Logging in HPC: Al...

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21st international Conference on Parallel and Distributed computing (Euro-Par)

作者： Martsinkevich, Tatiana Ropars, Thomas Cappello, Franck Univ Paris 11 Inria Orsay France Inria Bordeaux France Argonne Natl Lab Argonne Lemont IL USA

ISBN: (纸本)9783319273082;9783319273075

Currently used global application checkpoint-restart will not be a suitable solution for HPC applications running on large scale as, given the predicted fault rates, it will impose a high load on the I/O subsystem and lead to inefficient resource usage. Combining application checkpointing with message logging is appealing as it allows restarting only the processes that actually failed. One major issue with message logging protocols is the high amount of memory required to store logs. In this work we propose to use additional dedicated resources to save the part of the logs that would not fit in the memory of a compute node. We show that, combined with a cluster-based hierarchical logging technique, only few dedicated nodes would be required to accommodate the memory requirement of message logging protocols. We additionally show that the proposed technique achieves a reasonable performance overhead.

关键词： high-performance computing Fault tolerance Message logging Hierarchical message-logging protocols Dedicated resources

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Mascar: Speeding up GPU warps by reducing memory pitstops

Mascar: Speeding up GPU warps by reducing memory pitstops

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IEEE symposium on high-performance computer architecture

作者： Ankit Sethia D. Anoushe Jamshidi Scott Mahlke Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI University of Michigan Ann Arbor MI US

With the prevalence of GPUs as throughput engines for data parallel workloads, the landscape of GPU computing is changing significantly. Non-graphics workloads with high memory intensity and irregular access patterns are frequently targeted for acceleration on GPUs. While GPUs provide large numbers of compute resources, the resources needed for memory intensive workloads are more scarce. Therefore, managing access to these limited memory resources is a challenge for GPUs. We propose a novel Memory Aware Scheduling and Cache Access Re-execution (Mascar) system on GPUs tailored for better performance for memory intensive workloads. This scheme detects memory saturation and prioritizes memory requests among warps to enable better overlapping of compute and memory accesses. Furthermore, it enables limited re-execution of memory instructions to eliminate structural hazards in the memory subsystem and take advantage of cache locality in cases where requests cannot be sent to the memory due to memory saturation. Our results show that Mascar provides a 34% speedup over the baseline round-robin scheduler and 10% speedup over the state of the art warp schedulers for memory intensive workloads. Mascar also achieves an average of 12% savings in energy for such workloads.

关键词： Processor scheduling Kernel Graphics processing units Memory management Random access memory Hardware

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Leveraging MPI-3 Shared-Memory Extensions for Efficient PGAS Runtime Systems 21st

Leveraging MPI-3 Shared-Memory Extensions for Efficient PGAS...

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21st international Conference on Parallel and Distributed computing (Euro-Par)

作者： Zhou, Huan Idrees, Kamran Gracia, Jose Univ Stuttgart High Performance Comp Ctr Stuttgart HLRS D-70174 Stuttgart Germany

ISBN: (纸本)9783662480960;9783662480953

The relaxed semantics and rich functionality of one-sided communication primitives of MPI-3 makes MPI an attractive candidate for the implementation of PGAS models. However, the performance of such implementation suffers from the fact, that current MPI RMA implementations typically have a large overhead when source and target of a communication request share a common, local physical memory. In this paper, we present an optimized PGAS-like runtime system which uses the new MPI-3 shared-memory extensions to serve intra-node communication requests and MPI-3 one-sided communication primitives to serve inter-node communication requests. The performance of our runtime system is evaluated on a Cray XC40 system through low-level communication benchmarks, a random-access benchmark and a stencil kernel. The results of the experiments demonstrate that the performance of our hybrid runtime system matches the performance of low-level RMA libraries for intra-node transfers, and that of MPI-3 for inter-node transfers.

关键词： MPI One-sided communication Remote-memory access RMA Partitioned global address space PGAS

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SNNAP: Approximate computing on programmable SoCs via neural acceleration

SNNAP: Approximate computing on programmable SoCs via neural...

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IEEE symposium on high-performance computer architecture

作者： Thierry Moreau Mark Wyse Jacob Nelson Adrian Sampson Hadi Esmaeilzadeh Luis Ceze Mark Oskin University of Washington Georgia Institute of Technology

Many applications that can take advantage of accelerators are amenable to approximate execution. Past work has shown that neural acceleration is a viable way to accelerate approximate code. In light of the growing availability of on-chip field-programmable gate arrays (FPGAs), this paper explores neural acceleration on off-the-shelf programmable SoCs. We describe the design and implementation of SNNAP, a flexible FPGA-based neural accelerator for approximate programs. SNNAP is designed to work with a compiler workflow that configures the neural network's topology and weights instead of the programmable logic of the FPGA itself. This approach enables effective use of neural acceleration in commercially available devices and accelerates different applications without costly FPGA reconfigurations. No hardware expertise is required to accelerate software with SNNAP, so the effort required can be substantially lower than custom hardware design for an FPGA fabric and possibly even lower than current “C-to-gates” high-level synthesis (HLS) tools. Our measurements on a Xilinx Zynq FPGA show that SNNAP yields a geometric mean of 3.8× speedup (as high as 38.1×) and 2.8× energy savings (as high as 28 x) with less than 10% quality loss across all applications but one. We also compare SNNAP with designs generated by commercial HLS tools and show that SNNAP has similar performance overall, with better resource-normalized throughput on 4 out of 7 benchmarks.

关键词： Field programmable gate arrays Acceleration Neurons Biological neural networks System-on-chip Topology

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TECA: Petascale Pattern Recognition for Climate Science 16th

TECA: Petascale Pattern Recognition for Climate Science

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16th international Conference on computer Analysis of Images and Patterns (CAIP)

作者： Prabhat Byna, Surendra Vishwanath, Venkatram Dart, Eli Wehner, Michael Collins, William D. Univ Calif Berkeley Lawrence Berkeley Natl Lab Berkeley CA 94720 USA Argonne Natl Lab Argonne IL 60439 USA

ISBN: (纸本)9783319231174;9783319231167

Climate Change is one of the most pressing challenges facing humanity in the 21st century. Climate simulations provide us with a unique opportunity to examine effects of anthropogenic emissions. high-resolution climate simulations produce "Big Data": contemporary climate archives are approximate to 5PB in size and we expect future archives to measure on the order of Exa-Bytes. In this work, we present the successful application of TECA (Toolkit for Extreme Climate Analysis) framework, for extracting extreme weather patterns such as Tropical Cyclones, Atmospheric Rivers and Extra-Tropical Cyclones from TB-sized simulation datasets. TECA has been run at full-scale on Cray XE6 and IBM BG/Q systems, and has reduced the runtime for pattern detection tasks from years to hours. TECA has been utilized to evaluate the performance of various computational models in reproducing the statistics of extreme weather events, and for characterizing the change in frequency of storm systems in the future.

关键词： Pattern detection Climate science high performance computing Parallel I/O Data mining Petascale

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Domain knowledge based energy management in handhelds

Domain knowledge based energy management in handhelds

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IEEE symposium on high-performance computer architecture

作者： Nachiappan Chidambaram Nachiappan Praveen Yedlapalli Niranjan Soundararajan Anand Sivasubramaniam Mahmut T. Kandemir Ravi Iyer Chita R. Das The Pennsylvania State University Intel Corp.

Energy management in handheld devices is becoming a daunting task with the growing number of accelerators, increasing memory demands and high computing capacities required to support applications with stringent QoS needs. Current DVFS techniques that modulate power states of a single hardware component, or even recent proposals that manage multiple components, can lose out opportunities for attaining high energy efficiencies that may be possible by leveraging application domain knowledge. Thus, this paper proposes a coordinated multi-component energy optimization mechanism for handheld devices, where the energy profile of different components such as CPU, memory, GPU and IP cores are considered in unison to trigger the appropriate DVFS state by exploiting the application domain knowledge. Specifically, we show that for the important class of frame-based applications, the domain knowledge - frame processing rates, component utilization and available slack - can be used to decide effective DVFS states for each component from among the numerous choices. With such knowledge, rather than a brute force search of all speed setting choices, we propose two simpler heuristics, called Greedy policy and Kaldor-Hicks compensation policy, to make the decisions at frame boundaries. Our evaluations with 7 commonly-used Android apps show that our domain-aware coordinated DVFS policies have 23% better energy efficiency than the conventionally used Android governors, and are within ~9% of an optimal policy that does not drop any frames.

关键词： IP networks Power measurement computer aided manufacturing System-on-chip Hardware Games Energy management

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Coordinated static and dynamic cache bypassing for GPUs

Coordinated static and dynamic cache bypassing for GPUs

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IEEE symposium on high-performance computer architecture

作者： Xiaolong Xie Yun Liang Yu Wang Guangyu Sun Tao Wang Center for Energy-Efficient Computing and Applications Peking University China Department of EE Tsinghua University China

ISBN: (纸本)9781479989317

The massive parallel architecture enables graphics processing units (GPUs) to boost performance for a wide range of applications. Initially, GPUs only employ scratchpad memory as on-chip memory. Recently, to broaden the scope of applications that can be accelerated by GPUs, GPU vendors have used caches in conjunction with scratchpad memory as on-chip memory in the new generations of GPUs. Unfortunately, GPU caches face many performance challenges that arise due to excessive thread contention for cache resource. Cache bypassing, where memory requests can selectively bypass the cache, is one solution that can help to mitigate the cache resource contention problem. In this paper, we propose coordinated static and dynamic cache bypassing to improve application performance. At compile-time, we identify the global loads that indicate strong preferences for caching or bypassing through profiling. For the rest global loads, our dynamic cache bypassing has the flexibility to cache only a fraction of threads. In CUDA programming model, the threads are divided into work units called thread blocks. Our dynamic bypassing technique modulates the ratio of thread blocks that cache or bypass at run-time. We choose to modulate at thread block level in order to avoid the memory divergence problems. Our approach combines compile-time analysis that determines the cache or bypass preferences for global loads with run-time management that adjusts the ratio of thread blocks that cache or bypass. Our coordinated static and dynamic cache bypassing technique achieves up to 2.28X (average 1.32X) performance speedup for a variety of GPU applications.

关键词： Instruction sets Graphics processing units Synchronization Kernel Pipelines Arrays System-on-chip

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A Dual-FPGA architecture with Rejuvenation for Realtime Applications

A Dual-FPGA Architecture with Rejuvenation for Realtime Appl...

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Pacific Rim international symposium on Dependable computing

作者： Saysanasongkham Aromhack Satoshi Fukumoto Shuto Daigaku Tokyo Hachioji Tokyo JP Graduate School of System Design Tokyo Metropolitan University Hino Tokyo Japan

This paper focuses on FPGA for realtime applications and proposes a redundant configuration scheme with rejuvenation on a dual-FPGA architecture to handle SEUs. Duplication check is utilized to detect errors within the FPGAs. Rollback and re-computation will be attempted when the error is detected. If the error remains, the rejuvenation will be triggered. The proposed architecture consists of two identical FPGAs. When one FPGA has to undergo a rejuvenation process, the other will be available to operate the system. This ensures the real time computing constraint of an application.

关键词： Field programmable gate arrays computer architecture Real-time systems Fault tolerance Fault tolerant systems Single event upsets

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Accelerating Lattice Boltzmann Applications with OpenACC 21st

Accelerating Lattice Boltzmann Applications with OpenACC

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21st international Conference on Parallel and Distributed computing (Euro-Par)

作者： Calore, Enrico Kraus, Jiri Schifano, Sebastiano Fabio Tripiccione, Raffaele Univ Ferrara Dip Fis & Sci Terra I-44100 Ferrara Italy Ist Nazl Fis Nucl Ferrara Italy NVIDIA GmbH Wurselen Germany Univ Ferrara Dip Matemat & Informat I-44100 Ferrara Italy

ISBN: (纸本)9783662480960;9783662480953

An increasingly large number of HPC systems rely on heterogeneous architectures combining traditional multi-core CPUs with power efficient accelerators. Designing efficient applications for these systems has been troublesome in the past as accelerators could usually be programmed only using specific programming languages - such as CUDA - threatening maintainability, portability and correctness. Several new programming environments try to tackle this problem;among them OpenACC offers a high-level approach based on directives. In OpenACC, one annotates existing C, C++ or Fortran codes with compiler directive clauses to mark program regions to offload and run on accelerators and to identify available parallelism. This approach directly addresses code portability, leaving to compilers the support of each different accelerator, but one has to carefully assess the relative costs of potentially portable approach versus computing efficiency. In this paper we address precisely this issue, using as a test-bench a massively parallel Lattice Boltzmann code. We implement and optimize this multi-node code using OpenACC and OpenMPI. We also compare performance with that of the same algorithm written in CUDA, OpenCL and C for GPUs, Xeon-Phi and traditional multi-core CPUs, and characterize through an accurate time model its scaling behavior on a large cluster of GPUs.

关键词： OpenACC OpenMPI Lattice Boltzmann methods Accelerator computing performance analysis

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Balancing reliability, cost, and performance tradeoffs with FreeFault

Balancing reliability, cost, and performance tradeoffs with ...

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IEEE symposium on high-performance computer architecture

作者： Dong Wan Kim Mattan Erez Electrical and Computer Engineering Department The University of Texas at Austin

Memory errors have been a major source of system failures and fault rates may rise even further as memory continues to scale. This increasing fault rate, especially when combined with advent of integrated on-package memories, may exceed the capabilities of traditional fault tolerance mechanisms or significantly increase their overhead. In this paper, we present FreeFault as a hardware-only, transparent, and nearly-free resilience mechanism that is implemented entirely within a processor and can tolerate the majority of DRAM faults. FreeFault repurposes portions of the last-level cache for storing retired memory regions and augments a hardware memory scrubber to monitor memory health and aid retirement decisions. Because it relies on existing structures (cache associativity) for retirement/remapping type repair, FreeFault has essentially no hardware overhead. Because it requires a very modest portion of the cache (as small as 8KB) to cover a large fraction of DRAM faults, FreeFault has almost no impact on performance. We explain how FreeFault adds an attractive layer in an overall resilience scheme of highly-reliable and highly-available systems by delaying, and even entirely avoiding, calling upon software to make tradeoff decisions between memory capacity, performance, and reliability.

关键词： Random access memory Retirement Maintenance engineering Hardware Error correction codes Software Memory management

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