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检索条件"任意字段=22nd ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPoPP 2017"

共 16 条记录，以下是1-10 订阅

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An Architecture and programming Model for Accelerating parallel Commutative Computations via Privatization 22

An Architecture and Programming Model for Accelerating Paral...

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22nd acm sigplan symposium on principles and practice of parallel programming (ppopp)

作者： Balaji, Vignesh Tirumala, Dhruva Lucia, Brandon Carnegie Mellon Univ Pittsburgh PA 15213 USA

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Recovering Performance for Vector-based Machine Learning on Managed Runtime 22

Recovering Performance for Vector-based Machine Learning on ...

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22nd acm sigplan symposium on principles and practice of parallel programming (ppopp)

作者： Wu, Mingyu Guan, Haibing Zang, Binyu Chen, Haibo Shanghai Jiao Tong Univ Inst Parallel & Distributed Syst Shanghai Key Lab Scalable Comp & Syst Shanghai Peoples R China

ISBN: (纸本)9781450344937

The explosive growth of data and the demand for learning useful information from such data have stimulated a crossdisciplinary area named big learning, which leverages a cluster of commodity machines to run machine learning applications on large datasets. Those applications are usually implemented on high-level programming frameworks [1-4], which are running atop managed runtimes. Since the applications usually involve many iterations of computation over input data, the frameworks will cache them for performance consideration. In this work, we investigate a set of vectorbased machine learning applications in Spark MLlib [3] and find that cached datasets have a strong impact on overall efficiency. Copyright is held by the Owner/Author(s).

关键词： Learning systems

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Using Butterfly-Patterned Partial Sums to Draw from Discrete Distributions 17

Using Butterfly-Patterned Partial Sums to Draw from Discrete...

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22nd acm sigplan symposium on principles and practice of parallel programming (ppopp)

作者： Steele, Guy L., Jr. Tristan, Jean-Baptiste Oracle Labs Ludhiana Punjab India

ISBN: (纸本)9781450344937

We describe a SIMD technique for drawing values from multiple discrete distributions, such as sampling from the random variables of a mixture model, that avoids computing a complete table of partial sums of the relative probabilities. A table of alternate ("butterfly-patterned") form is faster to compute, making better use of coalesced memory accesses;from this table, complete partial sums are computed on the fly during a binary search. Measurements using CUBA 7.5 on an NVIDIA Titan Black GPU show that this technique makes an entire machine-learning application that uses a Latent Dirichlet Allocation topic model with 1024 topics about about 13% faster (when using single-precision floating-point data) or about 35% faster (when using double precision floating-point data) than doing a straightforward matrix transposition after using coalesced accesses.

关键词： butterfly coalesced memory access discrete distribution GPU latent Dirichlet allocation LDA machine learning multithreading memory bottleneck parallel computing random sampling SIMD transposed memory access

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Synchronized-by-Default Concurrency for Shared-Memory Systems 17

Synchronized-by-Default Concurrency for Shared-Memory System...

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22nd acm sigplan symposium on principles and practice of parallel programming (ppopp)

作者： Battig, Martin Gross, Thomas R. Swiss Fed Inst Technol Dept Comp Sci Zurich Switzerland

ISBN: (纸本)9781450344937

We explore a programming approach for concurrency that synchronizes all accesses to shared memory by default. Synchronization takes place by ensuring that all program code runs inside atomic sections even if the program code has external side effects. Threads are mapped to atomic sections that a programmer must explicitly split to increase concurrency. A naive implementation of this approach incurs a large amount of overhead. We show how to reduce this overhead to make the approach suitable for realistic application programs on existing hardware. We present an implementation technique based on a special-purpose software transactional memory system. To reduce the overhead, the technique exploits properties of managed, object-oriented programming languages as well as intraprocedural static analyses and uses field-level granularity locking in combination with transactional I/O to provide good scaling properties. We implemented the synchronized-by-default (SBD) approach for the Java language and evaluate its performance for six programs from the DaCapo benchmark suite. The evaluation shows that, compared to explicit synchronization, the SBD approach has an overhead between 0.4% and 102% depending on the benchmark and the number of threads, with a mean (geom.) of 23.9%.

关键词： Atomic blocks Concurrency parallel programming Synchronization Transactional memory

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Proceedings of the acm sigplan symposium on principles and practice of parallel programming, ppopp

Proceedings of the ACM SIGPLAN Symposium on Principles and P...

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22nd acm sigplan symposium on principles and practice of parallel programming, ppopp 2017

ISBN: (纸本)9781450344937

The proceedings contain 46 papers. The topics discussed include: layout lock: a scalable locking paradigm for concurrent data layout modifications;understanding the GPU microarchitecture to achieve bare-metal performance tuning;an efficient abortable-locking protocol for multi-level NUMA systems;contention in structured concurrency: provably efficient dynamic non-zero indicators for nested parallelism;noise injection techniques to expose subtle and unintended message races;thread data sharing in cache: theory and measurement;exploiting vector and multicore parallelism for recursive, data- and task-parallel programs;isoefficiency in practice: configuring and understanding the performance of task-based applications;processor-oblivious record and replay;and groute: an asynchronous multi-GPU programming model for irregular computations.

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POSTER: Provably Efficient Scheduling of Cache-Oblivious Wavefront Algorithms 17

POSTER: Provably Efficient Scheduling of Cache-Oblivious Wav...

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22nd acm sigplan symposium on principles and practice of parallel programming (ppopp)

作者： Chowdhury, Rezaul Ganapathi, Pramod Tang, Yuan Tithi, Jesmin Jahan SUNY Stony Brook Dept Comp Sci Stony Brook NY 11794 USA Fudan Univ Sch Software Shanghai Key Lab Intelligent Informat Proc Shanghai Peoples R China Intel Corp Santa Clara CA USA

ISBN: (纸本)9781450344937

Standard cache-oblivious recursive divide-and-conquer algorithms for evaluating dynamic programming recurrences have optimal serial cache complexity but often have lower parallelism compared with iterative wavefront algorithms due to artificial dependencies among subtasks. Very recently cache-oblivious recursive wavefront (COW) algorithms have been introduced which do not have any artificial dependencies. Though COW algorithms are based on fork-join primitives, they extensively use atomic operations, and as a result, performance guarantees provided by state-of-the-art schedulers for programs with fork-join primitives do not apply. In this work, we show how to systematically transform standard cache-oblivious recursive divide-and-conquer algorithms into recursive wavefront algorithms to achieve optimal parallel cache complexity and high parallelism under state-of-the-art schedulers for fork join programs. Unlike COW algorithms these new algorithms do not use atomic operations. Instead, they use closed-form formulas to compute at what time each recursive function must be launched in order to achieve high parallelism without losing cache performance. The resulting implementations are arguably much simpler than implementations of known COW algorithms.

关键词： recursive wavefront cache-oblivious parallel divide-and-conquer dynamic programming

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Isoefficiency in practice: Configuring and Understanding the Performance of Task-based Applications 17

Isoefficiency in Practice: Configuring and Understanding the...

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22nd acm sigplan symposium on principles and practice of parallel programming (ppopp)

作者： Shudler, Sergei Calotoiu, Alexandru Hoefler, Torsten Wolf, Felix Tech Univ Darmstadt Darmstadt Germany Swiss Fed Inst Technol Zurich Switzerland

ISBN: (纸本)9781450344937

Task-based programming offers an elegant way to express units of computation and the dependencies among them, making it easier to distribute the computational load evenly across multiple cores. However, this separation of problem decomposition and parallelism requires a sufficiently large input problem to achieve satisfactory efficiency on a given number of cores. Unfortunately, finding a good match between input size and core count usually requires significant experimentation, which is expensive and sometimes even impractical. In this paper, we propose an automated empirical method for finding the isoefficiency function of a task based program, binding efficiency, core count, and the input size in one analytical expression. This allows the latter two to be adjusted according to given (realistic) efficiency objectives. Moreover, we not only find (i) the actual isoefficiency function but also (ii) the function one would yield if the program execution was free of resource contention and (iii) an upper bound that could only be reached if the program was able to maintain its average parallelism throughout its execution. The difference between the three helps to explain low efficiency, and in particular, it helps to differentiate between resource contention and structural conflicts related to task dependencies or scheduling. The insights gained can be used to co-design programs and shared system resources.

关键词： parallel programming tasking isoefficiency performance modeling performance analysis co-design

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Tapir: Embedding Fork-Join parallelism into LLVM's Intermediate Representation 17

Tapir: Embedding Fork-Join Parallelism into LLVM's Intermedi...

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22nd acm sigplan symposium on principles and practice of parallel programming (ppopp)

作者： Schardl, Tao B. Moses, William S. Leiserson, Charles E. MIT Comp Sci & Artificial Intelligence Lab 32 Vassar St Cambridge MA 02139 USA

ISBN: (纸本)9781450344937

This paper explores how fork-join parallelism, as supported by concurrency platforms such as Cilk and OpenMP, can be embedded into a compiler's intermediate representation (IR). Mainstream compilers typically treat parallel linguistic constructs as syntactic sugar for function calls into a parallel runtime. These calls prevent the compiler from performing optimizations across parallel control constructs. Remedying this situation is generally thought to require an extensive reworking of compiler analyses and code transformations to handle parallel semantics. Tapir is a compiler IR that represents logically parallel tasks asymmetrically in the program's control flow graph. Tapir allows the compiler to optimize across parallel control constructs with only minor changes to its existing analyses and code transformations. To prototype Tapir in the LLVM compiler, for example, we added or modified about 6000 lines of LLVM's 4-million-line codebase. Tapir enables LLVM's existing compiler optimizations for serial code - including loop-invariant-code motion, common-subexpression elimination, and tail-recursion elimination - to work with parallel control constructs such as spawning and parallel loops. Tapir also supports parallel optimizations such as loop scheduling.

关键词： Cilk compiling control-flow graph fork-join parallelism LLVM multicore OpenMP optimization parallel computing serial semantics Tapir

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Exploiting Vector and Multicore parallelism for Recursive, Data- and Task-parallel Programs 17

Exploiting Vector and Multicore Parallelism for Recursive, D...

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22nd acm sigplan symposium on principles and practice of parallel programming (ppopp)

作者： Ren, Bin Krishnamoorthy, Sriram Agrawal, Kunal Kulkarni, Milind Coll William & Mary Williamsburg VA 23187 USA Pacific Northwest Natl Labs Richland WA USA Washington Univ St Louis St Louis MO USA Purdue Univ W Lafayette IN 47907 USA

ISBN: (纸本)9781450344937

Modern hardware contains parallel execution resources that are well-suited for data-parallelism vector units and task parallelism multicores. However, most work on parallel scheduling focuses on one type of hardware or the other. In this work, we present a scheduling framework that allows for a unified treatment of task- and data-parallelism. Our key insight is an abstraction, task blocks, that uniformly handles data-parallel iterations and task-parallel tasks, allowing them to be scheduled on vector units or executed independently as multicores. Our framework allows us to define schedulers that can dynamically select between executing task blocks on vector units or multicores. We show that these schedulers are asymptotically optimal, and deliver the maximum amount of parallelism available in computation trees. To evaluate our schedulers, we develop program transformations that can convert mixed data- and task-parallel programs into task block based programs. Using a prototype instantiation of our scheduling framework, we show that, on an 8-core system, we can simultaneously exploit vector and multicore parallelism to achieve 14 x-108 x speedup over sequential baselines.

关键词： Task parallelism Data parallelism General Scheduler

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Eunomia: Scaling Concurrent Search Trees under Contention Using HTM 17

Eunomia: Scaling Concurrent Search Trees under Contention Us...

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22nd acm sigplan symposium on principles and practice of parallel programming (ppopp)

作者： Wang, Xin Zhang, Weihua Wang, Zhaoguo Wei, Ziyun Chen, Haibo Zhao, Wenyun Fudan Univ Software Sch Shanghai Peoples R China Fudan Univ Shanghai Key Lab Data Sci Shanghai Peoples R China Fudan Univ Sch Comp Sci Shanghai Peoples R China Shanghai Jiao Tong Univ Inst Parallel & Distributed Syst Shanghai Peoples R China NYU Comp Sci Dept New York NY 10003 USA

ISBN: (纸本)9781450344937

While hardware transactional memory (HTM) has recently been adopted to construct efficient concurrent search tree structures, such designs fail to deliver scalable performance under contention. In this paper, we first conduct a detailed analysis on an HTM-based concurrent B+Tree, which uncovers several reasons for excessive HTM aborts induced by both false and true conflicts under contention. Based on the analysis, we advocate Eunomia, a design pattern for search trees which contains several principles to reduce HTM aborts, including splitting HTM regions with version based concurrency control to reduce HTM working sets, partitioned data layout to reduce false conflicts, proactively detecting and avoiding true conflicts, and adaptive con currency control. To validate their effectiveness, we apply such designs to construct a scalable concurrent B+Tree using HTM. Evaluation using key-value store benchmarks on a 20-core HTM-capable multi-core machine shows that Eunomia leads to 5X-11X speedup under high contention, while incurring small overhead under low contention.

关键词： Hardware Transactional Memory Concurrent Search Tree Opportunistic Consistency

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