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检索条件"任意字段=22nd ACM Symposium on Parallelism in Algorithms and Architectures"

共 16 条记录，以下是1-10 订阅

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SPAA'10 - Proceedings of the 22nd Annual symposium on parallelism in algorithms and architectures

SPAA'10 - Proceedings of the 22nd Annual Symposium on Parall...

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22nd acm symposium on parallelism in algorithms and architectures, SPAA'10

ISBN: (纸本)9781450300797

The proceedings contain 45 papers. The topics discussed include: buffer-space efficient and deadlock-free scheduling of stream applications on multi-core architectures;scheduling to minimize power consumption using submodular functions;collaborative scoring with dishonest participants;securing every bit: authenticated broadcast in radio networks;brief announcement: on speculative replication of transactional systems;data-aware scheduling of legacy kernels on heterogeneous platforms with distributed memory;basic network creation games;on the bit communication complexity of randomized rumor spreading;algorithms and application for grids and clouds;towards optimizing energy costs of algorithms for shared memory architectures;brief announcement: on regenerator placement problems in optical networks;best-effort group service in dynamic networks;and implementing and evaluating nested parallel transactions in software transactional memory.

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Towards Optimizing Energy Costs of algorithms for Shared Memory architectures 10

Towards Optimizing Energy Costs of Algorithms for Shared Mem...

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22nd acm symposium on parallelism in algorithms and architectures

作者： Korthikanti, Vijay Anand Agha, Gul Univ Illinois Dept Comp Sci Urbana IL USA

ISBN: (纸本)9781450300797

Energy consumption by computer systems has emerged as an important concern However, the energy consumed in executing an algorithm cannot be inferred from its performance alone it must be modeled explicitly This paper analyzes energy consumption of parallel algorithms executed on shared memory multicore processors Specifically, we develop a methodology to evaluate how energy consumption of a given parallel algorithm changes as the number of cores and their frequency is varied We use this analysis to establish the optimal number of cores to minimize the energy consumed by the execution of a parallel algorithm for a specific problem size while satisfying a given performance requirement We study the sensitivity of our analysis to changes in parameters such as the ratio of the power consumed by a computation step versus the power consumed in accessing memory The results show that the relation between the problem size and the optimal number of cores is relatively unaffected for a wide range of these parameters.

关键词： Energy Performance Parallel algorithms Shared Memory architectures

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Buffer-space Efficient and Deadlock-free Scheduling of Stream Applications on Multi-core architectures 10

Buffer-space Efficient and Deadlock-free Scheduling of Strea...

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22nd acm symposium on parallelism in algorithms and architectures

作者： Park, Jongsoo Dally, William J. Stanford Univ Comp Syst Lab Stanford CA 94305 USA

ISBN: (纸本)9781450300797

We present a scheduling algorithm of stream programs for multi-core architectures called team scheduling Compared to previous multi-core stream scheduling algorithms, team scheduling achieves 1) similar synchronization overhead, 2) coverage of a larger class of applications, 3) better control over buffer space, 4) deadlock-free feedback loops, and 5) lower latency We compare team scheduling to the latest stream scheduling algorithm, SGMS, by evaluating 14 applications on a multi-core architecture with 16 cores. Team scheduling successfully targets applications that cannot be validly scheduled by SGMS clue to excessive buffer requirement or deadlocks in feedback loops (e.g., GSM and W-cDmA) For applications that can be validly scheduled by SGMS, team scheduling shows on average 37% higher throughput within the same buffer space constraints

关键词： Compiler and Tools for Concurrent Programming Stream Programming Green Computing and Power-Efficient architectures Multi-core architectures

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Cache-Oblivious MPI All-to-All Communications on Many-Core architectures 22

Cache-Oblivious MPI All-to-All Communications on Many-Core A...

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22nd acm SIGPLAN symposium on Principles and Practice of Parallel Programming (PPoPP)

作者： Li, Shigang Zhang, Yunquan Hoefler, Torsten Chinese Acad Sci Inst Comp Technol SKL Comp Architecture Beijing Peoples R China Swiss Fed Inst Technol Dept Comp Sci Zurich Switzerland

ISBN: (纸本)9781450344937

In the many-core era, the performance of MPI collectives is more dependent on the intra-node communication component. However, the communication algorithms generally inherit from the inter-node version and ignore the cache complexity. We propose cache-oblivious algorithms for MPI all to-all operations, in which data blocks are copied into the receive buffers in Morton order to exploit data locality. Experimental results on different many-core architectures show that our cache-oblivious implementations significantly outperform the naive implementations based on shared heap and the highly optimized MPI libraries.

关键词： cache-oblivious algorithms MPI_Alltoall many-core

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Reliable logic mapping on nano-PLA architectures 12

Reliable logic mapping on nano-PLA architectures

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22nd Great Lakes symposium on VLSI, GLSVLSI'2012

作者： Zamani, Masoud Tahoori, Mehdi B. Northeastern University Boston United States Karlsruhe Institute of Technology Karlsruhe Germany

ISBN: (纸本)9781450312448

Programmable nano-architectures fabricated using bottom up self assembly are promising alternatives to CMOS circuits. However, extreme process variation and high defect rate are major challenges in this nanotechnology. In this paper, we present variation and defect aware logic mapping algorithms for these nano-architectures. Simulation results show that the proposed logic transformations and the mapping algorithms based on them can improve manufacturing yield by 65% with only 12.5% area overhead. Copyright 2012 acm.

关键词： Defects

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Annual acm symposium on parallelism in algorithms and architectures: Foreword

Annual ACM Symposium on Parallelism in Algorithms and Archit...

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Annual acm symposium on parallelism in algorithms and architectures 2010年 iii页

作者： Phillips, Cynthia Sandia National Laboratories United States

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Customizable compression architecture for efficient configuration in CGRAs 22

Customizable compression architecture for efficient configur...

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22nd IEEE Annual International symposium on Field-Programmable Custom Computing Machines ((FCCM)

作者： Jafri, Syed M. A. H. Tajammul, Adeel Daneshtalab, Masoud Hemani, Ahmed Paul, Kolin Ellervee, Peeter Plosila, Juha Tenhunen, Hannu Turku Ctr Comp Sci Turku Finland Tallinn Univ Technol Tallinn Estonia Univ Turku Turku Finland Royal Inst Technol Stockholm Sweden Indian Inst Technol Delhi India

ISBN: (纸本)9781479951116

Today, Coarse Grained Reconfigurable architectures (CGRAs) host multiple applications. Novel CGRAs allow each application to exploit runtime parallelism and time sharing. Although these features enhance the power and silicon efficiency, they significantly increase the configuration memory overheads. As a solution to this problem researchers have employed statistical compression, intermediate compact representation, and multicasting. Each of these techniques has different properties, and is therefore best suited for a particular class of applications. However, existing research only deals with these methods separately. In this paper we propose a morphable compression architecture that interleaves these techniques in a unique platform.

关键词： Compression algorithms Computer architecture Educational institutions Hardware Multicast communication Silicon Software Coarse grained reconfigurable architectures compression configuration compression energy aware systems multicast communication Compression algorithms Computer Architecture Educational institutions Computer hardware Silicon computer software compression Coarse-grained Reconfigurable Architecture time sharing

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Performance Implications of Global Virtual Time algorithms on a Knights Landing Processor 18

Performance Implications of Global Virtual Time Algorithms o...

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22nd IEEE/acm International symposium on Distributed Simulation and Real Time Applications (DS-RT)

作者： Eker, Ali Williams, Barry Mishra, Nitesh Thakur, Dushyant Chiu, Kenneth Ponomarev, Dmitry Abu-Ghazaleh, Nael SUNY Binghamton Binghamton NY 13901 USA Univ Calif Riverside Riverside CA 92521 USA

ISBN: (纸本)9781538650486

Recent studies investigated the performance of Parallel Discrete Event Simulation (PDES) on Intel Xeon Phi many-core processors, but generally reported underwhelming performance results, especially at high scales when all cores and thread contexts are fully loaded. While the lack of scalability in an earlier study on a Knights Corner (KC) processor is an artifact of physical limitations of the KC system, performance challenges on a Knights Landing (KNL) system partially stem from a slower global virtual time (GVT) computation algorithm used in that study. In this paper, we re-examine PDES performance on KNL under more efficient GVT algorithms to alleviate the GVT bottleneck. Specifically, we compare a synchronous GVT algorithm based on barrier synchronization, and two asynchronous GVT implementations: a modified Mattern's algorithm for shared memory systems and a recently-proposed wait-free algorithm. Using the ROSS simulator, we demonstrate that minimizing the GVT bottleneck results in significant improvement in scalability, allowing the simulation to scale with performance all the way to 250 threads (per chip). Interestingly, we observe that while for the balanced models the wait-free algorithm is a clear winner, barrier-based GVT provides significantly better results for imbalanced models executed at high scale. We also perform detailed simulation profiling to understand the underlying reasons for these performance trends.

关键词： Parallel Discrete Event Simulation Intel Xeon Phi Knights Landing Manycore architectures Performance Global Virtual Time

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Parallel pipelined FFT architectures with reduced number of delays 12

Parallel pipelined FFT architectures with reduced number of ...

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22nd Great Lakes symposium on VLSI, GLSVLSI'2012

作者： Ayinala, Manohar Parhi, Keshab K. University of Minnesota Union Street SE Minneapolis MN 55455 United States

ISBN: (纸本)9781450312448

This paper presents a novel approach to design four and eight parallel pipelined fast Fourier transform (FFT) architectures using folding transformation. The approach is based on use of decimation in time algorithms which reduce the number of delay elements by 33% compared to the decimation in frequency based designs. The number of delay elements required for an N-point FFT architecture is N -4 which is comparable to that of delay feedback schemes. The number of complex adders required is only 50% of those in the delay feedback designs. The proposed approach can be extended to any radix-2n based FFT algorithms. The proposed architectures are feed-forward designs and can be pipelined by more stages to increase the throughput. Further, a novel four parallel 128-point FFT architecture is derived using the proposed approach. It is shown that a radix- 24 4-parallel 128-point design requires 124 delay elements, 28 complex adders, and four full complex multipliers. Copyright 2012 acm.

关键词： Fast Fourier transforms

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A hybrid processing element based reconfigurable architecture for hashing algorithms

A hybrid processing element based reconfigurable architectur...

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22nd IEEE International Parallel and Distributed Processing symposium (IPDPS 2008)

作者： Sreedharan, Deepak Akoglu, Ali Univ Arizona Dept Elect & Comp Engn Reconfigurable Comp Lab Tucson AZ 85721 USA

ISBN: (纸本)9781424416936

Given the high computation demand for cryptography and hashing algorithms there is a need to develop flexible and high performance architectures. This paper proposes a methodology to derive processing elements as a starting point for the state-of-the-art reconfigurable computing and presents a case-study to show that application-specific reconfigurable computing has performance benefits close to fully-custom designs in addition to the intended reconfigurablity. We use hashing algorithms as a case study to propose a novel application-specific reconfigurable architecture based on a balanced mixture of coarse and fine grained processing elements with a tuned interconnect structure. For that purpose we introduce a methodology to derive hybrid grained processing elements and expose both fine and coarse grain parallelism based on a new common and recurring computation pattern extraction tool. After extracting the recurring patterns between SHA-1 and MD5 algorithms, we derive the unified interconnect architecture tailored to the control data dependencies of both the algorithms. That way the amount of reconfiguration on the proposed architecture when switching between the two algorithms is minimized. The proposed reconfigurable architecture is synthesized using the Synopsys design compiler targeted at TSMC 250 nm libraries. We compare its performance with ASIC technology on SHA-1 and MD5 algorithms. Results show that the proposed architecture which is reconfigurable between the two hashing algorithms has frequency of operation close to ASIC implementation of the individual algorithms for iterative and pipelined versions and results with 35% savings in area.

关键词： Reconfigurable architectures

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