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检索条件"任意字段=22nd IEEE International Symposium on On-Line Testing and Robust System Design, IOLTS 2016"

共 27 条记录，以下是1-10 订阅

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2016 ieee 22nd international symposium on On-line testing and robust system design, iolts 2016

2016 IEEE 22nd International Symposium on On-Line Testing an...

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22nd ieee international symposium on on-line testing and robust system design, iolts 2016

ISBN: (纸本)9781509015061

The proceedings contain 57 papers. The topics discussed include: on the robustness of DCT-based compression algorithms for space applications;a fault-tolerant sequential circuit design for SAFs and PDFs soft errors;an soft error propagation analysis considering logical masking effect on re-convergent path;analysis of BTI aging of level shifters;cache-aware reliability evaluation through LLVM-based analysis and fault injection;resilient random modulo cache memories for probabilistically-analyzable real-time systems;statistical analysis and comparison of 2T and 3T1D e-DRAM minimum energy operation;variations-tolerant 9T SRAM circuit with robust and low leakage SLEEP mode;how EDA can improve productivity in the assessment of functional safety;evaluating application-aware soft error effects in digital circuits without fault injections or probabilistic computations;hardware-simulation correlation of timing error detection performance of software-based error detection mechanisms;concurrent error detection and tolerance in Kalman filters using encoded state and statistical covariance checks;and on the influence of compiler optimizations in the fault tolerance of embedded systems.

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Temperature- and Aging-Resistant Inverter for robust and Reliable Time to Digital Circuit designs in a 65nm Bulk CMOS Process 22

Temperature- and Aging-Resistant Inverter for Robust and Rel...

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22nd ieee international symposium on on-line testing and robust system design (iolts)

作者： Tscherkaschin, Konstantin Hillebrand, Theodor Taddiken, Maike Paul, Steffen Peters-Drolshagen, Dagmar Univ Bremen Inst Electrodynam & Microelect ITEM Me Bremen Germany

ISBN: (纸本)9781509015061

Inverters are one of the most basic logic blocks and exhibit a strong temperature dependency. Additionally, degradation in CMOS transistors affects the performance of circuits over time and is strongly dependent on temperature during circuit operation. In order to design robust and reliable ring oscillators and time to digital converters, both temperature dependencies have to be considered. This work introduces a circuit design for a robust and resilient inverter and an analysis on its temperature-dependent aging characteristic. The implemented inverter is driven by a common-source amplifier to achieve high robustness against temperature variation and aging effects. Based on this, circuit designs for a ring oscillator and an inverter-based delay line for a time to digital converter has been implemented. The results show that the deviation of the delay for an inverter can be minimized from 13.2% for conventional inverter design to less than 2% for the temperature-and aging-resistant design over a wide temperature range from -40 degrees C to 150 degrees C and a stress time of ten years.

关键词： Reliability robustness Degradation Aging BTI Current-Starved Inverter Voltage Controlled Ring Oscillator Voltage Controlled Delay line Time to Digital Converter

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Variations-Tolerant 9T SRAM Circuit with robust and Low Leakage SLEEP Mode 22

Variations-Tolerant 9T SRAM Circuit with Robust and Low Leak...

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22nd ieee international symposium on on-line testing and robust system design (iolts)

作者： Jiao, Hailong Qiu, Yongmin Kursun, Volkan Eindhoven Univ Technol Elect Syst Grp Dept Elect Engn Dolech 2 NL-5612 AZ Eindhoven Netherlands Hong Kong Univ Sci & Technol Dept Elect & Comp Engn Kowloon Hong Kong Peoples R China

ISBN: (纸本)9781509015061

design of static random access memory (SRAM) circuits is challenging due to the degradation of data stability, weakening of write ability, increase of leakage power consumption, and exacerbation of process parameter variations with CMOS technology scaling. An asymmetrically ground-gated nine-transistor (9T) MTCMOS SRAM circuit is proposed in this paper for providing a low-leakage SLEEP mode with data retention capability. The worst-case static noise margin and write voltage margin are increased by up to 2.52x and 21.84%, respectively, with the asymmetrical 9T SRAM cells as compared to conventional six-transistor (6T) and eight-transistor (8T) SRAM cells under die-to-die process parameter variations in a 65nm CMOS technology. Furthermore, the mean values of static noise margin and write voltage margin are enhanced by up to 2.58x and 21.78% with the new 9T SRAM cells as compared with the conventional 6T and 8T SRAM cells under within-die process parameter fluctuations.

关键词： Transistors

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A Hybrid Self-diagnosis Mechanism with Defective Nodes Locating and Attack Detection for Parallel Computing systems 22

A Hybrid Self-diagnosis Mechanism with Defective Nodes Locat...

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22nd ieee international symposium on on-line testing and robust system design (iolts)

作者： Bu, Lake Karpovsky, Mark Boston Univ Reliable Comp Lab Elect & Comp Engn Boston MA 02215 USA

ISBN: (纸本)9781509015061

In recent years parallel computing has been widely employed for both science research and commercial applications. For parallel systems such as many-core or computer clusters, it is inevitable to have one or more computing node failures due to random errors or injected attacks. Usually a diagnosis mechanism is able to locate several defective nodes through a number of tests and the analysis of those test signatures (syndromes). Although this covers the cases caused by random errors, sophisticated attacks are still able to manipulate the outputs of each node, so that they will be masked and pass the diagnosis. Therefore in this paper we propose a hybrid self-diagnosis mechanism. We adopt a new type of analysis with the linear syndromes, which are able to locate up to a certain number of defective nodes caused by random errors. In addition to this, we introduce a new type of robust analysis of the non-linear syndromes, which is capable of detecting the attacks undetectable by the linear syndromes at a probability close to one. Moreover, since this hybrid self-diagnosis mechanism is on the data level which makes little distinction among different operating systems and programming languages, it can be migrated onto any other platforms conveniently.

关键词： self-diagnosis error locating error detection attack detection OLSC robust codes coding theory parallel computing linearity nonlinearity

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Automatic generation of stimuli for fault diagnosis in ieee 1687 networks 22

Automatic generation of stimuli for fault diagnosis in IEEE ...

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22nd ieee international symposium on on-line testing and robust system design, iolts 2016

作者： Cantoro, R. Montazeri, M. Sonza, M. Ghani Zadegan, F. Larsson, E. Reorda Politecnico di Torino Torino Italy Lund University Lund Sweden

ISBN: (纸本)9781509015061

The ieee 1687 standard describes reconfigurable structures allowing to flexibly access the instruments existing within devices (e.g., to support test, debug, calibration, etc.), by the use of configurable modules acting as controllable switches. The increasing adoption of this standard requires the availability of algorithms and tools to automate its usage. Since the resulting networks could inevitably be affected by defects which may prevent their correct usage, solutions allowing not only to test against these defects, but also to diagnose them (i.e., to identify the location of possible faults) are of uttermost importance. This paper proposes a method to automatically generate suitable test stimuli: by applying them and observing the output of the network one can not only detect possible faults, but also identify the fault responsible for the misbehavior. Experimental results gathered on a set of benchmark networks with a prototypical tool implementing the proposed techniques show the feasibility and provide a first idea about the length of the required input stimuli. © 2016 ieee.

关键词： Defects

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An on-line test solution for addressing interconnect shorts in on-chip networks

An on-line test solution for addressing interconnect shorts ...

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ieee symposium on On-line testing (iolts)

作者： Biswajit Bhowmik Jatindra Kumar Deka Santosh Biswas Department of Computer Science and Engineering Indian Institute of Technology Guwahati Guwahati India

This paper presents a scalable time optimized online test solution that addresses short faults in interconnects of an on-chip network (NoC) and observes the deep impact of these faults on NoC performance at large traf... 详细信息

ISBN: (纸本)9781509015085

关键词： testing Wires Clocks Mathematical model Routing Simulation

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Efficient fault tolerant parallel matrix-vector multiplications

Efficient fault tolerant parallel matrix-vector multiplicati...

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ieee symposium on On-line testing (iolts)

作者： Zhen Gao Pedro Reviriego Juan Antonio Maestro School of Electronic Information Engineering Tianjin University Tianjin China Escuela Politécnica Superior Universidad Antonio de Nebrija Madrid Spain

ISBN: (纸本)9781509015085

Parallel matrix processing is a typical operation in many systems, and in particular matrix-vector multiplication is one of the most common operations in modern digital signal processing and digital communication systems. This paper proposes a fault tolerant design for parallel matrix-vector multiplications. The scheme combines ideas from Error Correction Codes with the self-checking capability of matrix-vector multiplication.

关键词： Field-flow fractionation testing robustness system analysis and design

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Reusing logic masking to facilitate path-delay-based hardware Trojan detection

Reusing logic masking to facilitate path-delay-based hardwar...

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ieee symposium on On-line testing (iolts)

作者： Arash Nejat David Hely Vincent Beroulle LCIS Univ. Grenoble Alpes Valence France

ISBN: (纸本)9781509015085

Hardware Trojan (HT), Integrated Circuit (IC) piracy, and overproduction are three important threats which may happen in untrusted foundries. design changes against HTs, so-called design-For-Hardware-Trust (DFHT), are used in order to facilitate the HT detection. In addition, logic masking has been proposed against IC piracy and overproduction. In this work, we propose a DFHT method reusing the circuitry dedicated to logic masking in order to improve the HT detection based on the path delay analysis.

关键词： Manganese testing robustness system analysis and design

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On the robustness of DCT-based compression algorithms for space applications

On the robustness of DCT-based compression algorithms for sp...

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ieee symposium on On-line testing (iolts)

作者： S. Avramenko M. Sonza Reorda M. Violante G. Fey J.-G. Mess R. Schmidt Politecnico di Torino Torino Italy German Aerospace Center (DLR) Bremen Germany

ISBN: (纸本)9781509015085

High compression ratio is crucial to cope with the large amounts of data produced by telemetry sensors and the limited transmission bandwidth typical of space applications. A new generation of telemetry units is under development, based on Commercial Off-The-Shelf (COTS) components that may be subject to misbehaviors due to radiation-induced soft errors. The purpose of this paper is to study the impact of soft errors on different configurations of a discrete cosine transform (DCT)-based compression algorithm. This work's main contribution lies in providing some design guidelines.

关键词： Decision support systems Silicon testing robustness system analysis and design

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On the influence of compiler optimizations in the fault tolerance of embedded systems

On the influence of compiler optimizations in the fault tole...

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ieee symposium on On-line testing (iolts)

作者： Alejandro Serrano-Cases José Isaza-González Sergio Cuenca-Asensi Antonio Martínez-Álvarez Dept. of Computer Technology University of Alicante Alicante España

ISBN: (纸本)9781509015085

This paper proposes a method for tuning compilations to improve the size, execution time and reliability of the final application altogether. Our approach implements a genetic strategy with a multi-objective evolution that takes advantage of the NSGA-II algorithm for selecting the best compilations. Experiments show that reliability can be improved by efficiently exploring the compiler optimization options. As a consequence, our method enhances the application fault coverage from 3% to 6% and gets increments of MWTF from 15% to 45%.

关键词： Optimization Reliability Genetic algorithms Benchmark testing Sociology Statistics Measurement

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