Well-known for its efficient computing capabilities, FPGA-based architectures also have the potential for high flexibility with dynamic reconfiguration features. Yet, writing applications on these architectures is lab...
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Well-known for its efficient computing capabilities, FPGA-based architectures also have the potential for high flexibility with dynamic reconfiguration features. Yet, writing applications on these architectures is laborious, poorly portable and hardly scalable to multi-user and/or multi-FPGA systems, mainly because of a mixture of application related code and flexibility management code. In this paper, we propose a new abstraction layer, called Hardware Component Manager (HCM), which clearly separates the allocation of a hardware function from the control of a reconfiguration procedure, and guarantees the security of coexisting configurations. The implementation of this HCM layer on realistic simulation platforms demonstrates its ability to ease the management of FPGA flexibility while preserving performance and ensuring hardware function protection. HCM implementation and its simulation environment are open-source in the hope of reuse by the community.
Although the benefits of FPGAs for accelerating scientific codes are widely acknowledged, the use of FPGA accelerators in scientific computing is not widespread because reaping these benefits requires knowledge of har...
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Although the benefits of FPGAs for accelerating scientific codes are widely acknowledged, the use of FPGA accelerators in scientific computing is not widespread because reaping these benefits requires knowledge of hardware design methods and tools that is typically not available with domain scientists. A promising but hardly investigated approach is to develop tool flows that keep the common languages for scientific code (C,C++, and Fortran) and allow the developer to augment the source code with OpenMP-like directives for instructing the compiler which parts of the application shall be offloaded the FPGA accelerator. In this work we study whether the promise of effective FPGA acceleration with an OpenMP-like programming effort can actually be held. Our target system is the Convey HC-1 reconfigurable computer for which an OpenMP-like programming environment exists. As case study we use an application from computational nanophotonics. Our results show that a developer without previous FPGA experience could create an FPGA-accelerated application that is competitive to an optimized OpenMP-parallelized CPU version running on a two socket quad-core server. Finally, we discuss our experiences with this tool flow and the Convey HC-1 from a productivity and economic point of view.
This paper presents a motion estimation processor based on a dual-core architecture. Both cores are based on bit-serial adder trees. Memory structures are also described. This architecture is bit-precision reconfigura...
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This paper presents a motion estimation processor based on a dual-core architecture. Both cores are based on bit-serial adder trees. Memory structures are also described. This architecture is bit-precision reconfigurable. Performance results for several smartphones and tablets are presented. Furthermore, hardware results and comparison with other works are included. Real-time processing is achieved for all devices studied.
Demand is increasing daily for a robust VLSI chip that is useful in a radiation-rich environment. Optically reconfigurable gate arrays (ORGAs) have been developed to realize a radiation-tolerant Field Programmable Gat...
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Demand is increasing daily for a robust VLSI chip that is useful in a radiation-rich environment. Optically reconfigurable gate arrays (ORGAs) have been developed to realize a radiation-tolerant Field Programmable Gate Array (FPGA). The ORGA architecture is extremely robust against multi-event upsets. Moreover, it can recover from permanent errors resulting from a heavy total radiation dose. This paper presents demonstration results of a 16-configuration-context robust optically reconfigurable gate array with a reconfiguration speed-adjustment function.
We show how to encode, retrieve and process complex structures equivalent to First-Order logic (FOL) formulae, with Artificial Neural Networks (ANNs) designed for energy-minimization. The solution constitutes a bindin...
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An approach to the study of the reliability of complex quadrupole systems based on the use of intellectual simulation is offered, taking into account the mutual influence of components in the system.
An approach to the study of the reliability of complex quadrupole systems based on the use of intellectual simulation is offered, taking into account the mutual influence of components in the system.
A robust and manufacturable high-performance 100-nm gate length AlGaAs/InGaAs pseudomorphic High-Electron Mobility Transistor (pHEMT) process is presented.
A robust and manufacturable high-performance 100-nm gate length AlGaAs/InGaAs pseudomorphic High-Electron Mobility Transistor (pHEMT) process is presented.
The use of field programmable devices in security-critical applications is growing in popularity; in part, this can be attributed to their potential for balancing metrics such as efficiency and algorithm agility. Howe...
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The use of field programmable devices in security-critical applications is growing in popularity; in part, this can be attributed to their potential for balancing metrics such as efficiency and algorithm agility. However, in common with non-programmable alternatives, physical attack techniques such as fault and power analysis are a threat. We investigate a family of next-generation field programmable devices, specifically those based on the concept of time multiplexing, within this context: our results support the premise that extra, inherent flexibility in such devices can offer a range of possibilities for low-overhead, generic countermeasures against physical attack.
Parameterised configurations for FPGAs are configuration bitstreams of which part of the bits are defined as Boolean functions of parameters. By evaluating these Boolean functions using different parameter values, it ...
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Parameterised configurations for FPGAs are configuration bitstreams of which part of the bits are defined as Boolean functions of parameters. By evaluating these Boolean functions using different parameter values, it is possible to quickly and efficiently derive specialised configuration bitstreams with different properties. An important application of parameterised configurations is the generation of specialised configuration bitstreams for Dynamic Circuit Specialisation. Generating and using parameterised configurations requires a new FPGA tool flow. In this paper we present an algorithm for technology mapping of parameterised designs that can exploit the reconfigurability of the logic blocks and routing of the FPGA. This algorithm, called TCONMAP, is based on “Cut enumeration, cut ranking, node selection”. As part of it, a new method to calculate the feasibility of cuts based on the Binary Decision Diagrams (BDD) of their local function is proposed.
The paper deals with an optimal approaches used for programming of time consuming algorithms in digital signal processors. More precisely, the Texas Instruments' DSP with Very Long Instruction Word architecture is...
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The paper deals with an optimal approaches used for programming of time consuming algorithms in digital signal processors. More precisely, the Texas Instruments' DSP with Very Long Instruction Word architecture is taking into account. The principle of the optimal programming is based on new auxiliary tool which ensures the maximal functional units allocation. The properties of the programming method are proved by application of Fast Fourier Transform and they are compared with possibilities of Texas Instruments digital signal processing library. The proposed FFT implementation was tested on C6747 floating-point DSP and it is more efficient than official Texas Instruments library. Therefore, new functions can be used in high-performance computing systems.
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