It is well known that modeling with constraints networks require a fair expertise. Thus tools able to automatically generate such networks have gained a major interest. The major contribution of this paper is to set a...
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ISBN:
(纸本)9780769542638
It is well known that modeling with constraints networks require a fair expertise. Thus tools able to automatically generate such networks have gained a major interest. The major contribution of this paper is to set a new framework based on Inductive logicprogramming able to build a constraint model from solutions and non-solutions of related problems. The model is expressed in a middle-level modeling language. On this particular relational learning problem, traditional top-down search methods fall into blind search and bottom-up search methods produce too expensive coverage tests. Recent works in Inductive logicprogramming about phase transition and crossing plateau shows that no general solution can face all these difficulties. In this context, we have designed an algorithm combining the major qualities of these two types of search techniques. We present experimental results on some benchmarks ranging from puzzles to scheduling problems.
Mode-directed tabling amounts to using table modes to control what arguments are used in variant checking of subgoals and how answers are tabled. A mode can be min, max, + (input), - (output), or nt (non-tabled). Whil...
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ISBN:
(纸本)9780769542638
Mode-directed tabling amounts to using table modes to control what arguments are used in variant checking of subgoals and how answers are tabled. A mode can be min, max, + (input), - (output), or nt (non-tabled). While the traditional table-all approach to tabling is good for finding all answers, mode-directed tabling is well suited to dynamic programming problems that require selective answers. In this paper, we present three application examples of mode-directed tabling, namely, (1) hydraulic system planning, a dynamic programming problem, (2) the Viterbi algorithm in PRISM, a probabilistic logic reasoning and learning system, and (3) constraint checking in evaluating Answer Set Programs (ASP). For the Viterbi application, the feature of enabling a cardinality limit in a table mode declaration plays an important role. For a PRISM program and a set of data, the explanations may be too large to be completely stored and the cardinality limit allows for Viterbi inference based on a subset of explanations. The mode nt, which specifies an argument that can participate in the computation of a tabled predicate but is never tabled either in subgoal or answer tabling, is useful in constraint checking for the Hamilton cycle problem encoded as an ASP. These examples demonstrate the usefulness of mode-directed tabling.
Quantified constraint satisfaction problems have been the topic of an increasing number of studies for a few years. However, only sequential resolution algorithms have been proposed so far. This paper presents a paral...
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ISBN:
(纸本)9780769542638
Quantified constraint satisfaction problems have been the topic of an increasing number of studies for a few years. However, only sequential resolution algorithms have been proposed so far. This paper presents a parallel QCSP(+) solving algorithm based on a problem-partition approach. It then discuss about work distribution policies and presents several experimental results comparing several parameters.
In this paper, we examine logical formalisms with respect to contradictions and related notions. We deal with virtually any kind of logical formalisms, including those that fail to have any connective. We investigate ...
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ISBN:
(纸本)9780769542638
In this paper, we examine logical formalisms with respect to contradictions and related notions. We deal with virtually any kind of logical formalisms, including those that fail to have any connective. We investigate various properties, especially paraconsistency. Among the topics discussed are ways of specifying contradictions and, more generally, inconsistency, as well as a few criteria for paraconsistency. We further explore logical formalisms that overlap with fragments of classical logic, and provide a couple of formal results for them. A number of options about inconsistency are also discussed throughout the text, insisting on how contradictions can be specified either directly, or by way of reference to a fragment of classical logic. Importantly, the concept of undesirable conclusions is given a formal account, which is applied to most of the issues involved in this paper. A noticeable point is that we take into account not only features of the language, depending on the formalism, but also some aspects of inference, most notably the so-called Identity.
In cooperative intrusion detection, several intrusion detection systems (IDS), network analyzers, vulnerability analyzers and other analyzers are deployed in order to get an overview of the system under consideration....
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ISBN:
(纸本)9780769542638
In cooperative intrusion detection, several intrusion detection systems (IDS), network analyzers, vulnerability analyzers and other analyzers are deployed in order to get an overview of the system under consideration. In this case, the definition of a shared vocabulary describing the different information is prominent. Since these pieces of information are structured, we first propose to use description logics which ensure the reasoning decidability. Besides, the analyzers used in cooperative intrusion detection are not totally reliable. The second contribution of this paper is to handle these inconsistencies induced by the use of several analyzers using the so-called partial lexicographic inference.
We introduce a new plan repair method for problems cast as Mixed Integer Programs. In order to tackle the inherent complexity of these NP-hard problems, our approach relies on the use of Supervised Learning method for...
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ISBN:
(纸本)9780769542638
We introduce a new plan repair method for problems cast as Mixed Integer Programs. In order to tackle the inherent complexity of these NP-hard problems, our approach relies on the use of Supervised Learning method for the offline construction of a predictor which takes the problem's parameters as input and infers values for the discrete optimization variables. This way, the online resolution time of the plan repair problem can be greatly decreased by avoiding a large part of the combinatorial search among discrete variables. This contribution was motivated by the large-scale problem of intra-daily recourse strategy computation in electrical power systems. We report and discuss results on this benchmark, illustrating the different aspects and mechanisms of this new approach which provided close-to-optimal solutions in only a fraction of the computational time necessary for existing solvers.
作者:
Chen, WeiTan, ShaohuaPeking Univ
Sch EECS Minist Educ Key Lab High Confidence Software Technol Beijing 100871 Peoples R China Peking Univ
Key Lab Machine Percept Beijing 100871 Peoples R China
This paper addresses a new uncertainty set-interval random uncertainty set for robust Value-at-Risk optimization. The form of interval random uncertainty set makes it suitable for capturing the downside and upside dev...
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ISBN:
(纸本)9780769542638
This paper addresses a new uncertainty set-interval random uncertainty set for robust Value-at-Risk optimization. The form of interval random uncertainty set makes it suitable for capturing the downside and upside deviations of real-world data. These deviation measures capture distributional asymmetry and lead to better optimization results. We also apply our interval random chance-constrained programming to robust Value-at-Risk optimization under interval random uncertainty sets in the elements of mean vector. Numerical experiments with real market data indicate that our approach results in better portfolio performance.
We have experimentally investigated the trade-offs involved in thinning down the channel of III-V FETs with the ultimate goal of enhancing the electrostatic integrity and scalability of these devices. To do so, we hav...
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ISBN:
(纸本)9781424459209
We have experimentally investigated the trade-offs involved in thinning down the channel of III-V FETs with the ultimate goal of enhancing the electrostatic integrity and scalability of these devices. To do so, we have fabricated InAs HEMTs with a channel thickness of t(ch) = 5 nm and we have compared them against, InAs HEMTs with t(ch) = 10 nm. The fabricated thin-channel devices exhibit outstanding logic performance and scalability down to 40 nm in gate length. L-g = 40 nm devices exhibit S = 72 mV/dec, DIBL = 72 mV/V, and I-ON/I-OFF = 2.5 x 10(4), all at V-DS = 0.5 V. However, there are trade-offs of using a thin channel which manifest themselves in a higher source resistance, lower transconductance, and lower f(T) when compared with InAs HEMTs with t(ch) = 10 nm.
In this paper we introduce a new cardinality constraint: ORDEREDDISTRIBUTE. Given a set of variables, this constraint limits for each value v the number of times v or any value greater than v is taken. It extends the ...
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ISBN:
(纸本)9780769542638
In this paper we introduce a new cardinality constraint: ORDEREDDISTRIBUTE. Given a set of variables, this constraint limits for each value v the number of times v or any value greater than v is taken. It extends the global cardinality constraint, that constrains only the number of times a value v is taken by a set of variables and does not consider at the same time the occurrences of all the values greater than v. We design an algorithm for achieving generalized arc-consistency on ORDEREDDISTRIBUTE, with a time complexity linear in the sum of the number of variables and the number of values in the union of their domains. In addition, we give some experiments showing the advantage of this new constraint for problems where values represent levels whose overrunning has to be under control.
In this paper, MOS current mode logic (MCML) and dynamic current mode logic (DyCML) techniques are analyzed and applied to the generation of digital arithmetic circuits. A full adder structure is demonstrated, analyze...
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ISBN:
(纸本)9781612841519
In this paper, MOS current mode logic (MCML) and dynamic current mode logic (DyCML) techniques are analyzed and applied to the generation of digital arithmetic circuits. A full adder structure is demonstrated, analyzed and compared with equivalent CMOS, Domino and CPL structures and realized using 0.18 mu m CMOS technology operating with 1.5V and -1.5V supply voltages. Also, a four bit multiplier and a CORDIC block were analyzed and realized using MOS Current Mode logic. PSPICE simulation results of each realization have been demonstrated.
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