To maximize the design efficiency of the test chip area and maintain the high accuracy measurement requirement of resistors and capacitors, a 4K-cells resistive and charge-base capacitive test structure array is desig...
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ISBN:
(纸本)9781424442591
To maximize the design efficiency of the test chip area and maintain the high accuracy measurement requirement of resistors and capacitors, a 4K-cells resistive and charge-base capacitive test structure array is designed for CMOS logic process development, monitor and model. The test chip utilizes 4-terminal (one of 4 is strongly grounded) Kelvin force/sense measurement for resistive-type and charge-base capacitance measurement (CBCM) for capacitive-type test structures. With the aid of memory-addressing design scheme, any one of the device-under-test in an array can be randomly or sequentially selected for testing with all of them sharing a common probe pad group. To accelerate the testing speed, the address control signals of 8 test structure array are connected in parallel for synchronized parallel testing. A 32x16x8 test structure array has been implemented by utilizing a state-of-the-art logic process to demonstrate design feasibility. The results confirm the excellence of this architecture in measurement with 0.1fF for capacitive and 0.1ohm for resistive systematic errors, and 7 times testing speed improvement.
A trajectory-based point tracker using chaos evolutionary programming (CEP) algorithm is proposed in this paper. While motion constraints such as rigidity and small motion which are imposed by previous approaches are ...
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The project "Percorrendo Escrituras" (Walking Through Writings Project) has been developed at ECA-USP Fine Arts Department. Summarizing, it intends to study different structures of digital information that s...
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ISBN:
(纸本)9783642106422
The project "Percorrendo Escrituras" (Walking Through Writings Project) has been developed at ECA-USP Fine Arts Department. Summarizing, it intends to study different structures of digital information that share the same universe and are generators of a new aesthetics condition. The aim is to search which are the expressive possibilities of the computer among the algorithm functions and other of its specific properties. It is a practical, theoretical and interdisciplinary project where the study of programming evolutionary language, logic and mathematics take us to poetic experimentations. The focus of this research is the digital poetry, and it comes from poetics of permutation combinations and culminates with dynamic and complex systems, autonomous, multi-user and interactive, through agents generation derivations, filtration and emergent standards. This lecture will present artworks that use some mechanisms introduced by cybernetics and the notion of system in digital poetry that demonstrate the narrow relationship between poetics and the codes of computational logic.
There are many works on the satisfiability problem for various logics and constraint languages, such as SAT and Satisfiability Modulo Theories (SMT). On the other hand, the counting version of decision problems is als...
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ISBN:
(纸本)9783642029585
There are many works on the satisfiability problem for various logics and constraint languages, such as SAT and Satisfiability Modulo Theories (SMT). On the other hand, the counting version of decision problems is also quite important in automated reasoning. In this paper, we study a counting version of SMT, i.e., how to compute the volume of the solution space, given a set of Boolean combinations of linear constraints. The problem generalizes the model counting problem and the volume computation problem for convex polytopes. It has potential applications to program analysis and verification, as well as approximate reasoning, yet it has received little attention. We first give a straightforward method, and then propose an improved algorithm. We also describe two ways of incorporating theory-level lemma learning technique into the algorithm. They have been implemented, and some experimental results are given. Through an example program, we show that our tool can be used to compute how often a given program path is executed.
There is a common complaint that undergraduate programs in computing in many developing countries have not been preparing students sufficiently to become truly effective in the software industry. Although some program...
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There is a common complaint that undergraduate programs in computing in many developing countries have not been preparing students sufficiently to become truly effective in the software industry. Although some programs in computing are justified in paying little attention to programming, it is important to teach it properly to those wishing to develop software professionally. In order to produce qualified software developers, the focus should be not only on determining which programming-related subjects have to be taught, but also on training academicians to teach these subjects efficiently. In this paper we introduce an approach which tackles the former aspects.
We present the results of a data mining research on the use of GPS positions and speed of travel of vehicles in urban areas to determine optimal travel routes for emergency vehicles. A new approach using predictive pr...
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We present the results of a data mining research on the use of GPS positions and speed of travel of vehicles in urban areas to determine optimal travel routes for emergency vehicles. A new approach using predictive programming is presented. The approach focuses on using data mining of existing data as the key factor in the application logic where various decisions are to be made. The main appeal of such an approach is that the application logic evolves over time according to the application data. As the data changes the decisions soon follow. This gives the impression of intelligent behavior of the application.
Optical systems are becoming increasingly important as they tend to resolve many bottlenecks in the present age communications and electronics. Some common examples include their usage to meet high capacity link deman...
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This paper introduces a fuzzy logic based guidance architecture to a graph grammar framework for automated design of analog circuits. The grammar generates circuit topologies through a derivation tree. To boost this t...
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This paper introduces a fuzzy logic based guidance architecture to a graph grammar framework for automated design of analog circuits. The grammar generates circuit topologies through a derivation tree. To boost this tree based synthesis mechanism, smaller building blocks in the form of subtrees have been used for the purpose. These blocks have been automatically generated and their appropriateness for the design is updated runtime through the fuzzy system. Fuzzy logic helps to provide a smooth gradation for the relative merit of each block with respect to the design synthesized. The tool has been used to design an operational amplifier and a voltage controlled oscillator.
The objective of the 1st international Workshop on Advanced Software Development Tools and Techniques (WASDeTT-1) wits to provide interested researchers with a forum to share their tool building experiences and to exp...
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ISBN:
(纸本)9783642020469
The objective of the 1st international Workshop on Advanced Software Development Tools and Techniques (WASDeTT-1) wits to provide interested researchers with a forum to share their tool building experiences and to explore how tools can be built more effectively and efficiently. The theme for this workshop did focus on tools that target object-oriented languages and that are implemented with object-oriented languages. This workshop report provides a brief overview of the presented tools and of the discussions that took place. The presented tools, 15 in total, covered it broad range Of functionalities, among them: refactoring, modeling, behavioral specification, static and dynamic program checking, user interface composition, and program understanding. The discussion during the workshop centered around the following topics: language independent tools, tool building in an industrial context, tool building methodology, tool implementation language, and building tools with external code.
In sequential logic circuits the transient errors that occur in a particular time frame will propagate to consecutive time frames thereby making the device more vulnerable. In this work we propose a probabilistic erro...
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In sequential logic circuits the transient errors that occur in a particular time frame will propagate to consecutive time frames thereby making the device more vulnerable. In this work we propose a probabilistic error model for sequential logic that can measure the expected output error probability, given a probabilistic input space, that account for both spatial dependencies and temporal correlations across the logic, using a time evolving causal network. We demonstrate our error model using MCNC and ISCAS benchmark circuits and validate it with HSpice simulations. Our observations show that, significantly low individual gate error probabilities produce at least 5 fold higher output error probabilities. The average error percentage of our results with reference to HSpice simulation results is only 4.43%. Our observations show that the order of temporal dependency of error varies for different sequential circuits.
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