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Fast extraction of high-quality framework-specific models from application code

AUTOMATED SOFTWARE ENGINEERING 2009年第1期16卷 101-144页

作者： Antkiewicz, Michal Bartolomei, Thiago Tonelli Czarnecki, Krzysztof Univ Waterloo Generat Software Dev Lab Waterloo ON N2L 3G1 Canada

Framework-specific models represent the design of application code from the framework viewpoint by showing how framework-provided concepts are instantiated in the code. Retrieving such models quickly and precisely is necessary for practical model-supported software engineering, in which developers use design models for development tasks such as code understanding, verifying framework usage rules, and round-trip engineering. Also, comparing models extracted at different times of the software lifecycle supports software evolution tasks. We describe an experimental study of the static analyses necessary to automatically retrieve framework-specific models from application code. We reverse engineer a number of applications based on three open-source frameworks and evaluate the quality of the retrieved models. The models are expressed using framework-specific modeling languages (FSMLs), each designed for an open-source framework. For reverse engineering, we use prototype implementations of the three FSMLs. Our results show that for the considered frameworks and a large body of application code rather simple code analyses are sufficient for automatically retrieving framework-specific models with high precision and recall. Based on the initial results, we refine the static analyses and repeat the study on a larger set of applications to provide more evidence and confirm the results. The refined static analyses provide precision and recall of close to 100% for the analyzed applications.

关键词： Reverse engineering Framework-specific models Framework-specific modeling languages Static analysis Object-oriented frameworks Application programming interface API

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Cone Resynthesis ECO Methodology for Multi-Million Gate Designs

Cone Resynthesis ECO Methodology for Multi-Million Gate Desi...

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international conference on VLSI Design

作者： Suresh Raman Mike Lubyanitsky Intel Technologies India Private Limited Bangalore India Intel Corporation Santa Clara CA USA

In this paper, we talk about techniques to incrementally resynthesize logic cones within a large design impacted by multiple RTL changes in order to accommodate a late functional ECO. In design methodologies where the RTL is hierarchical and the post route netlist is flat, mapping a change in the behavioral description to the post layout netlist is very complicated and may not even be feasible if the RTL is not written in a synthesis friendly manner. We try to attack this problem by introducing a technique that causes minimum perturbation to the gate level netlist, thereby retaining to a large degree, the goodness metrics of timing convergence, routability and layout cleanliness that were achieved during the various design milestones. This paper talks about the cone resynthesis ECO methodology in detail and highlights its usefulness during tight product deliverable schedules.

关键词： Timing logic design Costs Routing Convergence Design engineering Fabrication Very large scale integration Scheduling logic gates

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Fast extraction of high-quality framework-specific models from application code

Fast extraction of high-quality framework-specific models fr...

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22nd international conference on Automated Software Engineering

作者： Antkiewicz, Michal Bartolomei, Thiago Tonelli Czarnecki, Krzysztof Univ Waterloo Generat Software Dev Lab Waterloo ON N2L 3G1 Canada

关键词： Reverse engineering Framework-specific models Framework-specific modeling languages Static analysis Object-oriented frameworks Application programming interface API

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Design-Space Exploration of Energy-Delay-Area Efficient Coarse-Grain Reconfigurable Datapath

Design-Space Exploration of Energy-Delay-Area Efficient Coar...

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international conference on VLSI Design

作者： Sohan Purohit Marco Lanuzza Stefania Perri Pasquale Corsonello Martin Margala Department of Electrical and Computer Engineering University of Massachusetts Lowell USA Department of Electronics Computer Science and Systems University of Calabria Rende Italy

This paper presents the VLSI design of a high data throughput, energy and area efficient data path targeted for DSP and multimedia applications. Three different implementations of the reconfigurable data path using static, dynamic domino and D3L logic styles are presented to serve as low power, high speed, and speed-energy optimized variants of the architecture. When implemented using ST Microelectronics 90 nm 1V CMOS technology, the proposed data path leads to a maximum supported clock frequency ranging from 917 MHz to 1.2 GHz with a dynamic power consumption @ 500 MHz ranging from 788 muW to 1.02 mW.

关键词： CMOS technology Very large scale integration Throughput Digital signal processing CMOS logic circuits Reconfigurable logic Microelectronics Clocks Frequency Energy consumption

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Piezoelectric Nanoswitch

Piezoelectric Nanoswitch

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IEEE international conference on Micro Electro Mechanical Systems

作者： D.C. Judy J.S. Pulskamp R.G. Polcawich L. Currano US Army Research Laboratory Adelphi MD USA

This paper details the design, fabrication, and measurement of a nano-scale mechanical switch. The switch uses lead zirconate titanate (PZT) actuators fabricated on silicon wafers and is intended to realize very low leakage complimentary mechanical logic elements. The switches were fabricated using an eleven step electron beam process using a novel dual electron beam photo resist technique to create gold air bridges. A normally closed switch was successfully demonstrated with switching times as fast as 17 ns, operating as low as 6 volt actuation.

关键词： Switches Electron beams Fabrication Mechanical variables measurement Titanium compounds Actuators Silicon logic Resists Gold

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RADJAM: A Novel Approach for Reduction of Soft Errors in logic Circuits

RADJAM: A Novel Approach for Reduction of Soft Errors in Log...

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international conference on VLSI Design

作者： Koustav Bhattacharya Nagarajan Ranganathan Department of Computer Science and Engineering University of South Florida Tampa FL USA

The task of achieving reliability against transient faults poses a significant challenge due to technology scaling trends. Several optimization techniques have been proposed in the literature for preventing soft errors in logic circuits. However, most approaches for avoiding soft errors in logic circuits have significant overheads in terms of delay, area or power. In this work, we propose a circuit level technique called RADJAM (RADiation JAMmer) to prevent soft errors, occurring due to radiation strikes, in logic cells. The RADJAM circuit when inserted at the output of a logic can reduce the generation of transient glitches significantly. Further, we propose an algorithm to insert RADJAM cells on selective nodes in a logic circuit. The algorithm uses signal logic probabilities and circuit slack for insertion of RADJAM cells on circuit nodes, thus improving the reliability of the logic circuit with minimal impact on the overall circuit delay. The proposed algorithm has been implemented and validated on the ISCAS85 benchmarks. Experimental results indicate that RADJAM optimized logic circuits can reduce soft error rates by around 39% with marginal delay, area and power overheads.

关键词： logic circuits Delay Circuit faults Voltage Electromagnetic transients Computer errors Combinational circuits Redundancy Low pass filters Space technology

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Boosting formal concepts to discover classification rules

Boosting formal concepts to discover classification rules

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22nd international conference on Industrial, Engineering and Other Applications of Applied Intelligent Systems, IEA/AIE 2009

作者： Meddouri, Nida Maddouri, Mondher Research Unit on Programming Campus Universitaire EL Manar Tunis - El Manar University Tunis 1060 Tunisia

ISBN: (纸本)3642025676

Supervised classification is a spot/task of data mining which consists in building a classifier from a set of examples labeled by their class (learning step) and then predicting the class of new examples with a classifier (classification step). In supervised classification, several approaches were proposed such as: Induction of Decision Trees, and Formal Concept Analysis. The learning of formal concepts is based, generally, on the mathematical structure of Galois lattice (or concept lattice). The complexity of generation of Galois lattice, limits the application fields of these systems. In this paper, we present several methods of supervised classification based on Formal Concept Analysis. We present methods based on concept lattice or sub lattice. We also present the boosting of classifiers, an emerging technique of classification. Finally, we propose the boosting of formal concepts: a new adaptive approach to build only a part of the lattice including the best concepts. These concepts are used as classification rules. Experimental results are given to prove the interest of the proposed method. © 2009 Springer Berlin Heidelberg.

关键词： Data mining

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A Low Power Architecture to Extend the Tuning Range of a Quadrature Clock

A Low Power Architecture to Extend the Tuning Range of a Qua...

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international conference on VLSI Design

作者： Ramen Dutta T.K. Bhattacharyya Electronics and Electrical Communication Engineering Department Indian Institute of Technology Kharagpur Kharagpur India

A low power architecture to extend the frequency range of quadrature clock is proposed. This architecture is based on a series of dividers. It can enhance the lower frequency limit of a Quadrature Voltage Controlled Oscillator (QVCO) clock to any arbitrarily small frequency. Based on the architecture a design is shown which enhances the low frequency range up to -90% of the center frequency, assuming the QVCO tuning range is +20%. The dividers are made of Dynamic Transmission Gate logic (DTGL) to reduce power consumption. Simulation result shows that the power consumption of the extender circuit, excluding the QVCO, is 2.1 mW from 1.2 V supply voltage at 3 GHz input frequency in 90 nm CMOS technology. The output jitter contribution by this circuit is 2 ps and 0.15 ps for mismatch and thermal noise respectively. Maximum output frequency achieved is 4.8 GHz for differential clock and 2.4 GHz for quadrature clock.

关键词： Clocks Frequency Tuning Energy consumption CMOS technology Voltage-controlled oscillators Circuit optimization logic gates CMOS logic circuits Circuit simulation

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Simultaneous Routing and Feedthrough Algorithm to Decongest Top Channel

Simultaneous Routing and Feedthrough Algorithm to Decongest ...

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international conference on VLSI Design

作者： Shashank Prasad Anuj Kumar Cadence Design Systems USA University of Wisconsin Madison USA

In macrocell based SoC design, a routing plan to decongest top channel is an important step during floor planning. While previous approaches attempt at reducing congestion of chip as a whole, there is no attempt to specifically decongest top channel. We present an algorithmic approach to decongest top channel by using very few feedthroughs. Results show that compared to conventional methods, we can decongest top channel by using 20% lesser feedthrough buffers, and better top channel routing resource utilization.

关键词： Routing Macrocell networks Algorithm design and analysis Pins Assembly Joining processes Timing Circuits logic design Very large scale integration

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MEMS Optical logic NOR Gate using Integrated Tunable Lasers

MEMS Optical Logic NOR Gate using Integrated Tunable Lasers

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IEEE international conference on Micro Electro Mechanical Systems

作者： B. Liu H. Cai X. M. Zhang J. Tamil Q. X. Zhang A. Q. Liu School of Electrical & Electronic Engineering Nanyang Technological University Singapore Department of Mechanical Engineering University of Maryland USA Institute of Microelectronics Singapore

This paper presents an optical logic NOR gate constructed by two MEMS tunable lasers and a Fabry-Perot (FP) laser chip. The key idea is that the FP chip is directly controlled by two tunable optical signals via the physical mechanism of injection locking. Compared with other fiber-based gating mechanisms, this logic operation only depends on the optical power without need for accurate phase matching or polarization control. In experiment, the logic NOR function is demonstrated successfully at 100 Mb/s with an extinction ratio of more than 20 dB, and it has a potential to reach higher speed of 10 Gb/s level. The work demonstrates a MEMS single-chip solution for optical logic gates with the advantages of compact footprint, simple optical alignment and easy integration, and may find potential applications in high-speed all-optical communication networks.

关键词： Micromechanical devices Integrated optics logic gates Tunable circuits and devices High speed optical techniques Fiber lasers Laser theory Optical control Optical fiber polarization Optical fiber networks

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