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international conference on VLSI Design

作者： Hiroyuki Yotsuyanagi Masaki Hashizume Toshiyuki Tsutsumi Koji Yamazaki Takashi Aikyo Yoshinobu Higami Hiroshi Takahashi Yuzo Takamatsu Institute of Technology and Science University of Tokushima Japan School of Science and Technology Meiji University Japan School of Information and Communication Meiji University Japan Graduate School of Science and Engineering Ehime University Japan

Open faults are difficult to test since the voltage at the floating line is unpredicted and depends on the voltage at the adjacent lines. The modeling for open faults with considering adjacent lines has been proposed. In this work, the 90 nm IC is designed and fabricated to evaluate how the voltage at adjacent lines affect the defective line. The open fault macros with a transmission gate and with an intentional break are included in the IC. The nine lines are placed in parallel in three layers to observe the effect of the coupling capacitance when an open occurs. The benchmark circuits with the open fault macro are also included in the IC. The simulation and experimental results show that the relationship between the floating line and the adjacent lines. The experimental results are also compared with the open fault model that calculate the weighted sum of voltages at the adjacent lines.

关键词： Circuit faults Voltage Capacitance Wires logic testing Very large scale integration Signal design Design engineering Integrated circuit testing Coupling circuits

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Design and Implementation of Fine-Grain Power Gating with Ground Bounce Suppression

Design and Implementation of Fine-Grain Power Gating with Gr...

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international conference on VLSI Design

作者： Kimiyoshi Usami Toshiaki Shirai Tasunori Hashida Hiroki Masuda Seidai Takeda Mitsutaka Nakata Naomi Seki Hideharu Amano Mitaro Namiki Masashi Imai Masaaki Kondo Hiroshi Nakamura Shibaura Institute of Technology Japan University of Tokyo Japan Keio University Japan Tokyo University of Agriculture슠and슠Technology Japan University of Electro-Communications Japan

This paper describes a design and implementation methodology for fine-grain power gating. Since sleep-in and wakeup are controlled in a fine granularity in run time, shortening the transition time between the sleep and active states is strongly required. In particular, shortening the wakeup time is essential because it affects the execution time and hence does the performance. However, this requirement makes suppression of the ground-bounce more difficult. We propose a novel technique to skew the wakeup timings of fine-grain local power domains to suppress the ground bounce. Delay of buffers driving power switches is skewed in the buffer tree by selectively downsizing them. We designed a MIPS R3000 based CPU core in a 90 nm CMOS technology and applied our technique to internal function units. Simulation results showed that our technique reduces the rush current to 47% over the case to turn-on the power switches simultaneously. This resulted in suppressing the ground bounce to 53 mV with 3.3 ns wakeup time. Simulation results from running benchmark programs showed that the total power dissipation for the function units was reduced by up to 15% at 25degC and by 62% at 100degC. Effectiveness in power savings is discussed from the viewpoint of the temperature-dependent break-even points and the consecutive idle time in the program.

关键词： Circuits logic gates Delay Central Processing Unit Power dissipation logic design CMOS technology Switches Very large scale integration Agriculture

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Power Reduction Techniques and Flows at RTL and System Level

Power Reduction Techniques and Flows at RTL and System Level

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international conference on VLSI Design

作者： Anmol Mathur Qi Wang Cadence Design Systems San Jose CA USA

Summary form only given. Power reduction is becoming a critical design criterion for ASIC/SOC designers. Reducing both dynamic and leakage power is imperative to meet power budgets for portable devices as well as to ensure that the systems that these ASICs meet their packaging and cooling costs. In addition, the power of an ASIC has a significant impact on its reliability and manufacturing yield. Traditionally, most automated power optimization tools have focused at gate-level and physical level optimizations. However, major power reductions are only possible by addressing power at the RTL and system levels. At these levels, it is possible to make the sequential modifications needed to reduce power and energy consumption via techniques like sequential clock gating, power gating, voltage/frequency scaling and other micro-architectural techniques. The focus of this tutorial will be on techniques for power reduction at the RTL and system level. It will also focus on expressing power intent at system and RTL levels and the flows needed to use that power intent in tools for functional verification, RTL-level optimization, logic synthesis and physical design. The following sections describe the key focus areas in the tutorial. We will start by discussing the key trends in the semiconductor industry and in CMOS technology and relate them to the need for power-aware design flows all the way from system-level design, through micro-architecture definition and RTL design and implementation. We will then present different power and energy metrics that are used at different points in the design cycle and for different purposes such as average power of a system, peak power of a system, energy per cycle etc. We will relate these metrics to their typical use and discuss when a metric should be used and optimized. State-of-the-art techniques for estimation of power and energy metrics will be presented including those for software power estimation, energy estimation for applications

关键词： Clocks State estimation Application specific integrated circuits CMOS technology Power system modeling Dynamic voltage scaling logic Packaging Cooling Costs

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Computer Science logic - 22nd international Workshop, CSL 2008 - 17th Annual conference of the EACSL, Proceedings

Computer Science Logic - 22nd International Workshop, CSL 20...

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22nd international Workshop on Computer Science logic, CSL 2008, and 17th Annual conference of the European Association for Computer Science logic, EACSL

ISBN: (纸本)3540875301

The proceedings contain 34 papers. The topics discussed include: the computability path ordering: the end of a quest;the joy of string diagrams;model transformations in decidability proofs for Monadic theories;an infinite automaton characterization of double exponential time;extensional uniformity for Boolean circuits;pure pointer programs with iteration;quantified positive temporal constraints;non-uniform Boolean constraint satisfaction problems with cardinality constraint;fractional collections with cardinality bounds, and mixed linear arithmetic with stars;a constructive semantic approach to cut elimination in type theories with axioms;proving infinitude of prime numbers using binomial coefficients;quantitative game semantics for linear logic;and a characterization of hypercoherent semantic correctness in multiplicative additive linear logic.

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Extended ASP Tableaux and rule redundancy in normal logic programs

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THEORY And PRACTICE OF logic programming 2008年第5-6期8卷 691-716页

作者： Jarvisalo, Matti Oikarinen, Emilia Aalto Univ Dept Informat & Comp Sci FI-02015 Helsinki Finland

We introduce an extended tableau calculus for answer set programming (ASP). The proof system is based on the ASP tableaux defined in the work by Gebser and Schaub (Tableau calculi for answer set programming. In Proceedings of the 22nd international conference on logic programming (ICLP 2006), S. Etalle and M. Truszczynski, Eds. Lecture Notes in Computer Science, vol. 4079. Springer, 11-25) with an added extension rule. We investigate the power of Extended ASP Tableaux both theoretically and empirically. We study the relationship of Extended ASP Tableaux with the Extended Resolution proof system defined by Tseitin for sets of clauses, and separate Extended ASP Tableaux from ASP Tableaux by giving a polynomial-length proof for a family of normal logic programs {Pi(n)} for which ASP Tableaux has exponential-length minimal proofs with respect to n. Additionally, Extended ASP Tableaux imply interesting insight into the effect of program simplification on the lengths of proofs in ASP. Closely related to Extended ASP Tableaux, we empirically investigate the effect of redundant rules on the efficiency of ASP solving.

关键词： Answer set programming tableau method extension rule proof complexity problem structure

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No silver bullet: Software engineering reloaded

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IEEE SOFTWARE 2008年第1期25卷 91-94页

作者： Fraser, Steven Mancl, Dennis Cisco Research Alcatel-Lucent

Information about several papers discussed at the 22nd international conference on Object-Oriented programming, Systems, Languages, and Applications (OOPSLA 2007) in Montreal, Quebec is presented. The conference was in celebration of the 20th anniversary of the paper entitled 'No Silver Bullet: Essence and Accidents of Software Engineering,' by Fred Brooks. The panelists discussed whether Brooks' assumptions that the complexity of software was not accidental.

关键词： conferenceS & conventions COMPUTER programming SOFTWARE engineering INFORMATION technology TECHNOlogicAL complexity CONGRESSES

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22nd Workshop on (Constraint) logic programming, WLP 2008

22nd Workshop on (Constraint) Logic Programming, WLP 2008

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22nd Workshop on (Constraint) logic programming, WLP 2008

The proceedings contain 11 papers. The special focus in this conference is on logic programming The topics include: An integrated development environment for JCHR;well-supported models of disjunctive logic programs;it's like datalog for RDF;a pattern-based answer to the versatile web challenge;declarative programming of user interfaces;propagating credibility in answer set programs;implementing hierarchical hybrid automata using constraint logic programming;a generalised program-correspondence framework;a workforce-scheduling application using a CP-AI-hybrid;a generalised finite domain constraint solver for SWI-prolog and an efficient hypothesis-finding system implemented with deduction and dualization.

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Estimation of Possible Reaction States in Metabolic Pathways using Inductive logic programming

Estimation of Possible Reaction States in Metabolic Pathways...

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22nd international Workshops on Advanced Information Networking and Applications

作者： Yamamoto, Yoshitaka Inoue, Katsumi Doncescu, Andrei Grad Univ Adv Studies Dept Informat Chiyoda Ku 2-1-2 Hitotsubashi Tokyo 1018430 Japan Natl Inst Informat Chiyoda Ku Tokyo 1018430 Japan CNRS LAAS F-31007 Toulouse France

ISBN: (纸本)9781424442331

This paper provides a method for estimating states Of enzyme reactions in metabolic pathways. We rst introduce a new model based on the logical viewpoint of enzyme function. The proposed model logically represents causal relations between concentration changes of metabolites and enzyme activities. When we observe the concentration changes of metabolites, we can assume which enzyme reactions are accelerated under the model. This computation can be realized using Inductive logic programming (ILP), which can nd a hypothesis that accounts for given observations with a background theory. In this paper we use CF-induction, which is an ILP technique and has a unique feature that can integrate inductive and abductive inferences. CF-induction can compute not only possible reaction states that can explain the observations, but also general rules that are missing in the current background theory Then, we perform experiments with simple metabolic pathways, and con rm that CF-induction can both estimate states of reactions and discover new causal rules.

关键词： Metabolites

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Bilateral Bargaining Game and Fuzzy logic in the System Handling SLA-Based Workflow

Bilateral Bargaining Game and Fuzzy Logic in the System Hand...

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22nd international Workshops on Advanced Information Networking and Applications

作者： Quan, Dang Minh Altmann, Joern Int Univ Germany Sch Informat Technol D-76646 Bruchsal Germany Seoul Natl Univ TEMEP Sch Engn Seoul 151742 South Korea

ISBN: (纸本)9781424442331

In the business Grid, the owner of a workflow is assumed to ask an SLA Workflow broker to execute the workflow for him. The price for executing a workflow on the Grid is negotiated between the user and the broker Determining a price that satisfies both, the user and the SLA workflow broker, is a difficult task. This paper proposes a method using bilateral bargaining game model based on fuzzy logic to determine the price that the user and the broker could accept after the first negotiation round. We also analyze many parameters affecting the price determination process. The validation results show that the approach is suitable with business rules.

关键词： Fuzzy logic

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Advanced dynamic programming in semiring and hypergraph frameworks

Advanced dynamic programming in semiring and hypergraph fram...

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22nd international conference on Computational Linguistics, Coling 2008

作者： Huang, Liang Department of Computer and Information Science University of Pennsylvania United States

ISBN: (纸本)9781905593446

Dynamic programming (DP) is an important class of algorithms widely used in many areas of speech and language processing. Recently there have been a series of work trying to formalize many instances of DP algorithms under algebraic and graph-theoretic frameworks. This tutorial surveys two such frameworks, namely semirings and directed hypergraphs, and draws connections between them. We formalize two particular types of DP algorithms under each of these frameworks: the Viterbi-style topological algorithms and the Dijkstra-style best-first algorithms. Wherever relevant, we also discuss typical applications of these algorithms in Natural Language Processing. © 2008 Licensed under the Creative Commons.

关键词： Dynamic programming

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