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WikiSym'07, ISMM'07, HPC-GECO/CompFrame'07, DLS'07 - 22nd ACM SIGPLAN conference on Object-Oriented programming Systems and Applications Companion, OOPSLA'07

作者： Landre, Einar Wesenberg, Harald Olmheim, Jorn Statoil ASA Application Development Center Forusbeen 50 N-4035 Stavanger Norway Statoil ASA Energy Trading Support Rotvoll N-7005 Trondheim Norway Statoil ASA Application Development Center Rotvoll N-7005 Trondheim Norway

ISBN: (纸本)9781595938657

In this paper we present the experience gained and lessons learned when the IT department at Statoil ASA, a large Oil and Gas company in Norway, applied Domain-Driven design techniques in combination with agile software development practices to assess the software architecture of our next generation oil trading and supply chain application. Our hypothesis was that the use of object oriented techniques, Domain-Driven design and a proper objectrelational mapping tool would significantly improve the performance and reduce the code base compared with current legacy systems. The legacy system is based on several Oracle databases serving a variety of clients written in Java, Gupta Centura Team Developer and HTML. The databases have a layer of business logic written in PL/SQL offering various system services to the clients. To validate our new object oriented software architecture, we re-implemented one of the most computationally heavy and data intensive services using Test First and Domain-Driven design techniques. The resulting software was then tested on a set of servers with a representative subset of data from the production environment. We found that using these techniques improved our software architecture with respect to performance as well as code quality when running on top of our Oracle databases. We also tested the switch to an object database from Versant and achieved additional performance gains.

关键词： Object oriented programming

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STARC: Static Analysis for Efficient Repair of Complex Data

STARC: Static Analysis for Efficient Repair of Complex Data

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22nd Annual ACM SIGPLAN international conference on Object-Oriented programming, Systems, Languages, and Applications, OOPSLA'07

作者： Elkarablieh, Bassem Sarfraz, Khurshid Vu, Duy McKinley, Kathryn S. University of Texas Austin United States

ISBN: (纸本)1595937862

Data structure corruptions are insidious bugs that reduce reliability of software systems. Constraint-based data repair promises to help programs recover from crippling corruption errors. Prior work repairs variety of relatively small data structures, usually with of nodes. present STARC which uses static analysis to repair structures with tens of thousands of nodes. Given a predicate method that describes the integrity constraints a structure, STARC statically analyzes the method to : (1) the recurrent fields, i.e., fields that the predicate uses to traverse the structure; and (2) local fieldconstraints, i.e., how the value of an object field is related to value of a neighboring object field. STARC executes the method on the structure and monitors its execution identify corrupt object fields, which STARC then repairs a systematic search of a neighborhood of the given. Each repair action is guided by the result of the analysis, which enables more efficient and effective compared to prior work. Experimental results show STARC can repair structures with tens of thousands of, up to 100 times larger than prior work. efficiency is probably not practical for very large structures in deployed systems, but opens a promising direction for future work. Copyright 2007 ACM.

关键词： Object oriented programming

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A Novel Flash-based FPGA Technology with Deep Trench Isolation

A Novel Flash-based FPGA Technology with Deep Trench Isolati...

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IEEE international Memory Workshop (IMW)

作者： Kyung Joon Han Nigel Chan Sungrae Kim Ben Leung Volker Hecht Brian Cronquist Danny Shum Armin Tilke Laura Pescini Martin Stiftinger Ronald Kakoschke Actcl Corp. Mountain View CA USA Infineon Technologies Dresden GmbH & Co. OHG Infineon Technologies AG Munich

A highly scalable flash-based Field Programmable Gate Array (FPGA) technology has been achieved with Deep Trench Isolation (DTI). The DTI allows for a reduced cell size and enables Independent Pwell (IPW) array operation. The IPW FPGA array operation requires less than + 10 V during Uniform Channel FN-FN programming and shows negligible gate disturb. Additionally, it eliminates Gate-Induced Drain Leakage (GIDL) during programming. Characterization of a FPGA cell and array with 90 nm design rules is demonstrated with excellent electrical characteristics.

关键词： Field programmable gate arrays Isolation technology Switches Diffusion tensor imaging Voltage logic programming logic devices Etching Nonvolatile memory Electric variables

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The First international workshop on patterns languages: Addressing Challenges (PLAC 2007)

The First international workshop on patterns languages: Addr...

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WikiSym'07, ISMM'07, HPC-GECO/CompFrame'07, DLS'07 - 22nd ACM SIGPLAN conference on Object-Oriented programming Systems and Applications Companion, OOPSLA'07

作者： Fayad, M.E. Chaing, Chia-Chu Chacin, Pablo Ramaswamy, Srini Sánchez-Ruíz, Arturo Nurcan, Selmin Dept. of Computer Engineering San José State University One Washington Square San José CA 95192 United States University of Arkansas Dept. of Computer Science 2801 South University Ave. Little Rock AR United States Technical University of Catalonya Departamento de Arquitectura de Computadores UPC Campus Nord Barcelona 08034 Spain Department of Computer Science Dickinson Hall Suite 515 University of Arkansas Little Rock AR 72204 United States School of Computing University of North Florida 4567 St Johns Bluff Rd. S. Jacksonville FL 32224-2669 United States Maítre de Conférences Centre de Recherche en Informatique Université Paris 1 Panthéon-Sorbonne France

ISBN: (纸本)9781595938657

A pattern language consists of a cascade or hierarchy of parts, linked closely together by patterns, which solve generically recurring problems that are associated with the parts. Each pattern has a title, and collectively the titles form a language for design [1] Pattern Languages are in life, simply a collection of interrelated patterns [2]. These interrelated patterns are combined in any way and combination to create new environments, where practitioners can solve context-specific ***, the concept of pattern languages has invaded over into the software engineering field, to describe prior experiences and the processes that stem from them, in a very simple language, where patterns are tactfully woven as a whole, and can be combined in any manner to solve a particular and complex problem. Yet, this process is still done in an ad-hoc manner and is not straightforward enough, to ease and speed up the software development ***, this workshop is driven forward by three main ***, how can we classify, develop, and utilize analysis and design patterns together towards the path of a problem resolution? Second, what is the "behind-the-"language that guides the sewing of patterns together as a whole? And third, how can we overcome and face challenges, other than patterns composition problems (patterns traceability, etc.) that can hinder the development of a system of patterns?

关键词： Object oriented programming

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MOP: An efficient and generic runtime verification frame

MOP: An efficient and generic runtime verification frame

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22nd Annual ACM SIGPLAN international conference on Object-Oriented programming, Systems, Languages, and Applications, OOPSLA'07

作者： Chen, Feng Ros¸u, Grigore University of Illinois Urbana-Champaign Urbana-Champaign United States

ISBN: (纸本)1595937862

Monitoring-Oriented programming (MOP1) [21, 18, 22, 19] is a formal framework for software development and analysis, in which the developer specifies desired properties using definable specification formalisms, along with code to execute when properties are violated or validated. The MOP framework automatically generates monitors from the specified properties and then integrates them together with the user-defined code into the original system. The previous design of MOP only allowed specifications without parameters, so it could not be used to state and monitor safety properties referring to two or more related objects. In this paper we propose a parametric specificationformalism-independent extension of MOP, together with an implementation of JavaMOP that supports parameters. In our current implementation, parametric specifications are translated into AspectJ code and then weaved into the application using off-the-shelf AspectJ compilers; hence, MOP specifications can be seen as formal or logical aspects. Our JavaMOP implementation was extensively evaluated on two benchmarks, Dacapo [14] and Tracematches [8], showing that runtime verification in general and MOP in particular are feasible. In some of the examples, millions of monitor instances are generated, each observing a set of related objects. To keep the runtime overhead of monitoring and event observation low, we devised and implemented a decentralized indexing optimization. Less than 8% of the experiments showed more than 10% runtime overhead; in most cases our tool generates monitoring code as efficient as the hand-optimized code. Despite its genericity, JavaMOP is empirically shown to be more efficient than runtime verification systems specialized and optimized for particular specification *** property violations were detected during our experiments; some of them are benign, others indicate defects in programs. Many of these are subtle and hard to find by ordinary testing. © 2007 ACM.

关键词： Object oriented programming

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A 1.8V 4Mb Floating-Gate NOR Type B4-Flash Test Chip for 100MB/s programming Speed

A 1.8V 4Mb Floating-Gate NOR Type B4-Flash Test Chip for 100...

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IEEE international Memory Workshop (IMW)

作者： M. Mihara Y. Kawajiri K. Kobayashi T. Ogura S. Shukuri N. Ajika M. Nakashima Genusion Inc. Amagasaki Hyogo Japan

A 1.8V 4 Mb floating-gate flash test chip utilizing back bias assisted band-to-band tunneling induced hot electron (B4-HE) injection mechanism (B4-Flash) has been fabricated. Double source line architecture (DSLA) and selective verifying method (SVM), applied to NOR arrayed B4-Flash enables to achieve 100 MB/s programming speed. The MLC capability of B4-Flash memory is also shown by realizing three levels of programmed Vth distribution with 0.8V width.

关键词： Testing Nonvolatile memory Voltage Support vector machines Flash memory Tunneling Electrons Pulse inverters logic programming Mechanical factors

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Defect-Tolerant Gate Macro Mapping & Placement in Clock-Free Nanowire Crossbar Architecture

Defect-Tolerant Gate Macro Mapping & Placement in Clock-Free...

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IEEE international Symposium on Defect and Fault Tolerance in VLSI Systems

作者： Ravi Bonam Yong-Bin Kim Minsu Choi Department of ECE University of Missouri Rolla Rolla MO USA Department of ECE Northeastern University Boston MA USA

ISBN: (纸本)0769528856

Recently, we proposed a new clock-free nanowire crossbar architecture based on a delay- insensitive paradigm called Null Convention logic (NCL). The proposed architecture has simple periodic structure that is suitable for non-deterministic nanoscale assembly and does not require a clock distribution network - so it is intrinsically free from timing-related failure modes. Even though the proposed architecture offers improved manufacturability, it is still not free from defects. This paper elaborates on the different programming techniques to map a given threshold gate macro on a random PGMB (Programmable Gate Macro Block) with predefined dimension. Defect-Aware and Defect Unaware approaches have been considered to map a given threshold gate onto a PGMB without affecting its functionality. Defect aware approach uses a defect map, gate table which help in efficient programming and also conservative use of resources. Defect unaware approach on the other hand is faster than defect aware approach, does not use defect maps and is not as efficient as defect aware approach. Parametric simulation results using MATLAB are used to show the programmability of these approaches under various circumstances.

关键词： Clocks Circuits Computer architecture Delay logic Registers Hysteresis USA Councils Manufacturing processes Robustness

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Specifying and verifying software 07

Specifying and verifying software

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Proceedings of the 22nd IEEE/ACM international conference on Automated Software Engineering

作者： K. Rustan M. Leino Microsoft Research Redmond WA

ISBN: (纸本)9781595938824

Software verification presents many challenges. One of these isproviding programmers with automated tool support for verification, another is providing specification support that captures common programming idioms. In this talk, I will discuss these two challenges, drawing from experience with building program verifiersfor Spec# and C. I will also give a demo of the Spec# programming system, which includes the automatic static program verifier Boogie.

关键词： languages verification automation tool support specification SMT solver programming

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Jeannie: Granting Java native interface developers their wishes

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ACM SIGPLAN NOTICES 2007年第10期42卷 19-38页

作者： Hirzel, Martin Grimm, Robert IBM Corp Thomas J Watson Res Ctr Yorktown Hts NY 10598 USA NYU New York NY USA

Higher-level languages interface with lower-level languages such as C to access platform functionality, reuse legacy libraries, or improve performance. This raises the issue of how to best integrate different languages while also reconciling productivity, safety, portability, and efficiency. This paper presents Jeannie, a new language design for integrating Java with C. In Jeannie, both Java and C code are nested within each other in the same file and compile down to JNI, the Java platform's standard foreign function interface. By combining the two languages' syntax and semantics, Jeannie eliminates verbose boiler-plate code, enables static error detection across the language boundary, and simplifies dynamic resource management. We describe the Jeannie language and its compiler, while also highlighting lessons from composing two mature programming languages.

关键词： design languages programming language composition Java C JNI foreign function interface xtc modular syntax Rats

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Static memory management for logic programming languages

Static memory management for logic programming languages

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22nd international conference on logic programming

作者： Phan, Quan Katholieke Univ Leuven Dept Comp Sci B-3001 Heverlee Belgium

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