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检索条件"任意字段=23rd International Conference on Algorithms and Architectures for Parallel Processing, ICA3PP 2023"

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Bayesian Optimization for Auto-tuning Convolution Neural Network on GPU 23rd

Bayesian Optimization for Auto-tuning Convolution Neural Net...

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23rd international conference on algorithms and architectures for parallel processing (ica3pp)

作者： Zhu, Huming Liu, Chendi Zhang, Lingyun Dong, Ximiao Xidian Univ Key Lab Intelligent Percept & Image Understanding Minist Educ Xian 710071 Peoples R China

ISBN: (纸本)9789819708109;9789819708116

GPU as a hardware processor plays an important role in the training of deep neural networks. However, when using GPUs for computation on convolutional neural network models, different combinations of GPU kernel configuration parameters have different performance. Therefore, this paper proposes BAGF, a bayesian auto-tuning framework for GPU kernels, which parameterizes the factors affecting the performance of GPU programs and uses bayesian optimization methods to search for the best parameters in the search space consisting of the parameters. Compared with other optimization algorithms, BAGF obtains excellent configuration parameters with fewer iterations. This paper analyzes the performance of BAGF on four benchmarks and compares with other common optimization algorithms. In addition, the performance improvement of each parameter configuration is analyzed. Finally, the BAGF was tested with the convolution layer of Alexnet, and the results of the Roofline model were analyzed. Compared with the original parameter configuration, the speed of BAGF was increased by 50.09%.

关键词： CNN parallel computing GPU Auto-tuning

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Dynamic Multi-bit parallel Computing Method Based on Reconfigurable Structure 23rd

Dynamic Multi-bit Parallel Computing Method Based on Reconfi...

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23rd international conference on algorithms and architectures for parallel processing (ica3pp)

作者： Jiang, Lin Liu, Shuai Zhu, Jiayang Shan, Rui Li, Yuancheng Xian Univ Sci & Technol Xian 710600 Shaanxi Peoples R China Xian Univ Posts & Telecommunicat Xian 710100 Shaanxi Peoples R China

ISBN: (纸本)9789819708000;9789819708017

Reconfigurable architecture has great potential in computation-intensive and memory-intensive applications due to its flexible information configuration. Aiming at the problem of low computing efficiency caused by the inconsistency between different granularity data and the underlying hardware structure in applications such as communication baseband signal processing, a parallel computing method supporting multi-bit data is proposed, and a dynamic granularity configuration structure used this method is designed based on reconfigurable array processors. The structure divides the calculation granularity into 8 bits, 16 bits, and 32 bits, and realizes four functions: data-combination, data-splitting, parallel-addition, and parallel-multiplication. These features increase the parallelism and flexibility of array structures. The experimental results show that the speedup ratio can reach 1.5 within a certain error range, the running time is reduced by about 20%, and the code complexity is also significantly reduced. In addition, the maximum operating frequency of the dynamic configuration circuit is 133.5 MHz by FPGA comprehensive implementation, which can realize the dynamic configuration of different granularity data in the calculation and achieve parallel computing of multi-bit data.

关键词： Reconfigurable Architecture parallel Computing Computing Granularity Array Processor

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Optimizing Pointwise Convolutions on Multi-core DSPs 1

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23rd international conference on algorithms and architectures for parallel processing (ica3pp)

作者： Wang, Yang Wang, Qinglin Pei, Xiangdong Mei, Songzhu Liu, Jie Natl Univ Def Technol Natl Key Lab Parallel & Distributed Comp Changsha 410073 Peoples R China Natl Univ Def Technol Lab Digitizing Software Frontier Equipment Changsha 410073 Peoples R China Beijing Inst Astronaut Syst Engn Beijing 100076 Peoples R China

ISBN: (数字)9789819708628

ISBN: (纸本)9789819708611;9789819708628

Pointwise convolutions are widely used in various convolutional neural networks, due to low computation complexity and parameter requirements. However, pointwise convolutions are still time-consuming like regular convolutions. As a result of increasing power consumption, low-power embedded processors have been brought into high-performance computing field, such as multi-core digital signal processors (DSPs). In this paper, we propose a high-performance multi-level parallel direct implementation of pointwise convolutions on multi-core DSPs in FT-M7032, a CPU-DSP heterogeneous prototype processor. The main optimizations include on-chip memory blocking, loop ordering, vectorization, register blocking, and multi-core parallelization. The experimental results show that the proposed direct implementation achieves much better performance than GEMM-based ones on FT-M7032, and a speedup of up to 79.26 times is achieved.

关键词： CNNs Pointwise Convolution Direct Convolution DSPs parallel algorithm

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LAST: An Efficient In-place Static Binary Translator for RISC architectures 1

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23rd international conference on algorithms and architectures for parallel processing (ica3pp)

作者： Lan, Yanzhi Hu, Qi Niu, Gen Li, Xinyu Wang, Liangpu Zhang, Fuxin Chinese Acad Sci State Key Lab Processors Inst Comp Technol Beijing Peoples R China Univ Chinese Acad Sci Beijing Peoples R China

ISBN: (数字)9789819708017

ISBN: (纸本)9789819708000;9789819708017

The lack of software has been a persistent issue for emerging instruction set architecture (ISA). To overcome this challenge, binary translation has emerged as a widely adopted solution, enabling programs written for older ISA to run on new ones. In the past, dynamic binary translation (DBT) was commonly utilized for software migration, but this technique required dynamic translation and often suffered from suboptimal efficiency. In contrast, Static binary translation (SBT) is an offline technique for translating binary code without runtime translation overhead. Existing SBT systems always employ address mapping tables to handle the address relocation problem, but this approach introduces performance overhead and leads to issues with indirect jump correctness. To address these limitations, we propose a novel static in-place instruction translation method for reduced-instruction set computing (RISC) architectures. This method ensures that the address of the guest program remains unchanged after translation, leveraging the regular length of various RISC instructions. We have implemented this method in a portable SBT tool called LAST, specifically designed to run MIPS or RISCV programs on the LoongArch platform. Based on the SPEC CPU2000 benchmark results, LAST achieves over 80% performance compared to the native LoongArch program, demonstrating its effectiveness and efficiency.

关键词： Static Binary Translation In-place instruction translation instrumentation

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gGMED: Towards GPU Accelerated Geometric Modeling Evaluation and Derivative Processes 23rd

gGMED: Towards GPU Accelerated Geometric Modeling Evaluation...

引用

23rd international conference on algorithms and architectures for parallel processing (ica3pp)

作者： Xuan, Zhibo Yang, Hailong Wang, Pengbo Sun, Xin Hao, Jiwei Duan, Shenglin Shi, Yongfeng Luan, Zhongzhi Qian, Depei Beihang Univ Sch Comp Sci & Engn Beijing Peoples R China Avic Digital Co Ltd Beijing Peoples R China

ISBN: (纸本)9789819707973;9789819707980

Geometric modeling algorithms serve as the fundamental computation of CAD/CAM software in the field of computer graphics. The evaluation and derivative processes, being an essential component of geometric modeling algorithms, significantly impact their overall performance. However, when dealing with scenarios involving high-precision models or large-scale datasets, the lack of parallel acceleration for geometric modeling computation results in prolonged computation time and low computation efficiency, hindering the satisfactory experience of user interaction. Although the massive parallelism of GPUs has been proved with successful performance acceleration in various application fields, it has not been effectively utilized for accelerating geometric modeling algorithms. In this paper, we propose gGMED, a GPU-based approach specifically designed for accelerating the evaluation and derivative processes in geometric modeling. To leverage the massive parallel capability of GPU, our approach provides several optimizations such as data reuse, bank conflict avoidance, and pipeline execution, for effectively improving the performance of evaluation and derivative processes. The experiment results on representative GPUs and various NURBS models demonstrate that our approach can achieve up to 10.18x and 34.56x performance speedup in end-to-end process and kernel computation respectively, compared to the state-of-the-art geometric modeling libraries.

关键词： Geometric modeling algorithms Evaluation Derivative parallel optimization GPU

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Distributed Generative Adversarial Networks for Fuzzy Portfolio Optimization 1

引用

23rd international conference on algorithms and architectures for parallel processing (ica3pp)

作者： Yang, Xueying Li, Chen Han, Zidong Lu, Zhonghua Chinese Acad Sci Comp Network Informat Ctr Beijing 100190 Peoples R China Univ Chinese Acad Sci Beijing 100049 Peoples R China

ISBN: (数字)9789819708598

ISBN: (纸本)9789819708581;9789819708598

Financial time series is one of the most important data in the field of economics and finance, and it is important to forecast and simulate such data effectively based on historical patterns and trends. Existing forecasting models mainly forecasting one-step ahead, and cannot retain the complex characteristics of financial time series data such as serial correlation and the long-term time-dependent relationship. On the other hand, the large-scale data makes the training of the deep learning models a time-consuming process. Therefore, how to forecast financial time series multi-step ahead efficiently has become a key point to improve the asset management capability. At the same time, constructing a fuzzy portfolio optimization for different distributions is also an important direction to improve the robustness of a portfolio model. This paper proposes a distributed financial time series simulating model AssetGANs that simulating multi-step ahead based on GANs, and apply GANs as a parameter simulation method to fuzzy portfolio optimization to provide users with better strategy choices. The paper carries on numerical experiments on real market stock data, compares the results with LSTM and achieves a training speedup of over 573 with 8 GPUs compared to the CPU version.

关键词： Generative Adversarial Networks Fuzzy Simulation Portfolio Optimization parallel computing

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SW-LeNet: Implementation and Optimization of LeNet-1 Algorithm on Sunway Bluelight II Supercomputer 1

引用

23rd international conference on algorithms and architectures for parallel processing (ica3pp)

作者： Ren, Zenghui Liu, Tao Liu, Zhaoyuan Tian, Min Guo, Ying Pan, Jingshan Qilu Univ Technol Shandong Comp Sci Ctr Natl Supercomp Ctr Jinan Shandong Acad Sci Jinan Peoples R China

ISBN: (数字)9789819708086

ISBN: (纸本)9789819708079;9789819708086

Nowadays, convolutional neural networks are representative of deep learning algorithms. With the development of convolutional neural networks, their network structures become more complex, and the number of parameters for training becomes larger and larger. The parallelization of convolutional neural network algorithms on multicore or many-core processors is essential for training convolutional neural networks. In this paper, we propose a parallel algorithm of LeNet-1 based on the Sunway Bluelight II supercomputer, named SW-LeNet. Moreover, we propose a two-level parallelization scheme, including thread-level optimization and process-level optimization. In thread-level optimization, the following optimization methods are used, including CPEs parallelism, hybrid scheme and DMA optimization, register optimization, and SIMD data parallelism. Data parallelism optimization and parameter packing optimization are used in process-level optimization. Compared with the original LeNet, SW-LeNet can achieve 4.94x speedups in a single core group. Moreover, SW-LeNet can be scaled up to 2,048 processes, with 133,120 cores, and achieves 84.93% parallel efficiency.

关键词： Sunway Many-core processor parallel optimization LeNet-1

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CAST: An Intricate-Scene Aware Adaptive Bitrate Approach for Video Streaming via parallel Training 1

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23rd international conference on algorithms and architectures for parallel processing (ica3pp)

作者： Li, Weihe Huang, Jiawei Liang, Yu Liu, Jingling Zhang, Wenlu Lyu, Wenjun Wang, Jianxin Univ Edinburgh Edinburgh EH8 9YL Midlothian Scotland Cent South Univ Changsha 410083 Peoples R China Univ Lancaster Lancaster LA1 4YW England Rutgers State Univ Newark NJ 08901 USA

ISBN: (数字)9789819708598

ISBN: (纸本)9789819708581;9789819708598

Adaptive Bitrate (ABR) algorithms have become increasingly important for delivering high-quality video content over fluctuating networks. Considering the complexity of video scenes, video chunks can be separated into two categories: those with intricate scenes and those with simple scenes. In practice, improving the quality of intricate chunks can lead to more significant improvements in Quality of Experience (QoE) than improving simple chunks. However, current schemes either assign equal priority to all chunks or optimize using a fixed linear-based reward function, making them inadequate for meeting real-world requirements. To tackle these limitations, this paper introduces a novel ABR approach that explicitly considers bitrate adaptation as the primary objective. The proposed approach, CAST (Complex-scene Aware bitrate algorithm via Self-play reinforcemenT learning), leverages the power of parallel computing with multiple agents to train a neural network, aiming to achieve superior video playback quality for intricate scenes while minimizing frequent freezing events. The extensive tracedriven evaluation and subjective test results demonstrate that CAST outperforms existing off-the-shelf schemes.

关键词： Video streaming Bitrate adaption parallel computing Self-play reinforcement learning Scene complexity

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SW-TRRM: parallel Optimization Research of the Random Ray Method Based on Sunway Bluelight II Supercomputer 23rd

SW-TRRM: Parallel Optimization Research of the Random Ray Me...

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23rd international conference on algorithms and architectures for parallel processing (ica3pp)

作者： Ren, Zenghui Liu, Tao Liu, Zhaoyuan Guo, Ying Pan, Jingshan Zhao, Dawei Wu, Xiaoming Yang, Meihong Qilu Univ Technol Shandong Comp Sci Ctr Natl Supercomp Ctr Jinan Shandong Acad Sci Jinan Peoples R China

ISBN: (纸本)9789819708079;9789819708086

The Random Ray Method (TRRM) is a new approach to solving partial differential equations (PDEs) based on the method of characteristics (MOC). It employs stochastic rather than deterministic discretization of characteristic tracks and can be used for the numerical simulation of nuclear reactors. In this paper, we propose SW-TRRM, a parallel optimization program for TRRM based on the Sunway Bluelight II Supercomputer for the first time. We present a two-level parallelization scheme that consists of thread-level and process-level optimization. At the thread-level, we introduce three schemes for speeding up within a single core group, including direct parallelization, parallelization by energy groups, and loop structure optimization. At the process-level, we implement task parallelization among multiple processes using domain replication. Moreover, we devise an algorithm to optimize the MPI collective communication across super-nodes. Experimental results show that SW-TRRM achieves a 17.40x speedup within a single core group compared to the original TRRM program. When scaled up to 2,048 processes and 133,120 cores, SW-TRRM maintains good strong and weak scalability.

关键词： High performance computing parallel optimization Sunway supercomputer The random ray method

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CMMR: A Composite Multidimensional Models Robustness Evaluation Framework for Deep Learning 1

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23rd international conference on algorithms and architectures for parallel processing (ica3pp)

作者： Liu, Wanyi Zhang, Shigeng Wang, Weiping Zhang, Jian Liu, Xuan Cent South Univ Sch Comp Sci Changsha 410083 Peoples R China Hunan Univ Coll Comp Sci & Elect Engn Changsha 410002 Peoples R China Sci & Technol Parallel & Distributed Proc Lab PDL Changsha 410073 Peoples R China

ISBN: (数字)9789819708086

ISBN: (纸本)9789819708079;9789819708086

Accurately evaluating the defense models against adversarial examples has been proven to be a challenging task. We have recognized the limitations of mainstream evaluation standards, which fail to account for the discrepancies in evaluation results arising from different adversarial attack methods, experimental setups, and metrics sets. To address these disparities, we propose the Composite Multidimensional Model Robustness (CMMR) evaluation framework, which integrates three evaluation dimensions: attack methods, experimental settings, and metrics sets. By comprehensively evaluating the model's robustness across these dimensions, we aim to effectively mitigate the aforementioned variations. Furthermore, the CMMR framework allows evaluators to flexibly define their own options for each evaluation dimension to meet their specific requirements. We provide practical examples to demonstrate how the CMMR framework can be utilized to assess the performance of models in enhancing robustness through various approaches. The reliability of our methodology is assessed through both practical examinations and theoretical validations. The experimental results demonstrate the excellent reliability of the CMMR framework and its significant reduction of variations encountered in evaluating model robustness in practical scenarios.

关键词： Robustness evaluation Adversarial attacks Adversarial machine learning

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