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检索条件"任意字段=23th International Conference on Architecture of Computing Systems 2010"

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37th international conference on architecture of computing systems, ARCS 2024

37th International Conference on Architecture of Computing S...

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37th international conference on architecture of computing systems, ARCS 2024

ISBN: (纸本)9783031661457

the proceedings contain 23 papers. the special focus in this conference is on architecture of computing systems. the topics include: the Power of Training: How Different Neural Network Setups Influence the Energy Demand;an Efficient Multi Quantile Regression Network with Ad Hoc Prevention of Quantile Crossing;Modifiable Artificial DNA - Change Your System’s ADNA at Any Time;From Structured to Unstructured: A Comparative Analysis of Computer Vision and Graph Models in Solving Mesh-Based PDEs;enhancing Maritime Behaviour Analysis through Novel Feature Engineering and Digital Shadow Modelling: A Case Study in the Kiel Fjord;Synthesizing Training Data for Intelligent Weed Control systems Using Generative AI;towards the Online Reconfiguration of a Dependable Distributed On-Board Computer;An Organic computing Approach for CARLA Simulator;Idle is the New Sleep: Configuration-Aware Alternative to Powering Off FPGA-Based DL Accelerators During Inactivity;On-the-Fly CT Image Pre-processing on MPSoC-FPGAs;AccProf: Increasing the Accuracy of Embedded Application Profiling Using FPGAs;accelerating WebAssembly Interpreters in Embedded systems through Hardware-Assisted Dispatching;Exploring the ARM Coherent Mesh Network Topology;comparison of a Binary Signed-Digit Adder with Conventional Binary Adder Circuits on Layout Level;Case Studies on the Impact and Challenges of Heterogeneous NUMA architectures for HPC;a Hierarchical Modeling Approach for Assessing the Reliability and Performability of Burst Buffers;Generative-Based Algorithm for Data Clustering on Hybrid Classical-Quantum NISQ architecture;improving Memory Dependence Prediction with Static Analysis;Atalanta: Open-Source RISC-V Microcontroller for Rust-Based Hard Real-Time systems;software-Based Erasure-Tolerant Coding with Buffering and Compression;determination of Optimal H-Matrices for 2-Bit Error Correcting Codes.

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2021 IEEE 23rd international conference on High Performance computing and Communications, 7th international conference on Data Science and systems, 19th international conference on Smart City and 7th international conference on Dependability in Sensor, Cloud and Big Data systems and Applications, HPCC-DSS-SmartCity-DependSys 2021

2021 IEEE 23rd International Conference on High Performance ...

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23rd IEEE international conference on High Performance computing and Communications, 7th IEEE international conference on Data Science and systems, 19th IEEE international conference on Smart City and 7th IEEE international conference on Dependability in Sensor, Cloud and Big Data systems and Applications, HPCC-DSS-SmartCity-DependSys 2021

ISBN: (纸本)9781665494571

the proceedings contain 343 papers. the topics discussed include: three-level compact caching for search engines based on solid state drives;a fine-grained volley gesture recognition method with direction independence;universal adversarial attack against 3d object tracking;efficient hardware redo logging for secure persistent memory;a cost-efficient metadata scheme for high-performance deduplication systems;high speed true random number generator controlled by logistic map;characterization and implication of edge WebAssembly runtimes;frend for edge servers: reduce server number! keeping service quality!;on-the-fly servers placement for online multiplayer games in the fog;advanced architecture design of high-radix router based on chiplet integration and IP reusability;embrace the conflicts: exploring the integration of single port memory in systolic array-based accelerators;visual sensitivity aware rate adaptation for video streaming via deep reinforcement learning;semi-supervised federated learning with non-IID data: algorithm and system design;on-demand intelligent routing algorithms for the deterministic networks;and distributed service placement in ultra-dense edge computing: a game-theoretical approach.

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12th international conference on High-Performance computing systems and Technologies in Scientific Research, Automation of Control and Production, HPCST 2022

12th International Conference on High-Performance Computing ...

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12th international conference on High-Performance computing systems and Technologies in Scientific Research, Automation of Control and Production, HPCST 2022

ISBN: (纸本)9783031237430

the proceedings contain 23 papers. the special focus in this conference is on High-Performance computing systems and Technologies in Scientific Research, Automation of Control and Production. the topics include: Ontology-Based Data Mining Platform for Diagnosing Sowing Quality of Wheat Seeds;algorithm for the Classification of Coronary Heart Disease Based on the Use of Symptom Complexes in the Cardiovascular Environment;business Process Designing of the Institutional Ranking System of Higher Education of the Kyrgyz Republic;evaluation of the Efficiency of the Vaccination Against Chickenpox Based on the Results of Simulation Modeling;hierarchical Volume Mesh Model of Heterogeneous Media Based on Non-Destructive Imaging Data;modeling a Potential Plant Habitat by Ensemble Machine Learning;adaptive Traffic Signal Control Based on a Macroscopic Model of the Transport Network;optimization and Robustization of Angular Motion Control of an Automatic Maneuverable Aerial Vehicle;synthesis of the Rational Analyzing Function for Feature Extraction of Signals from the Electrostatic Location System;architecture and CAD Software Solutions for PCB Design;application of Computer Numerical Control in Eddy-Current Study Methods;Open-Source Solution for Identification and Blocking of Anomalous BGP-4 Routing Information;Simulation of DDoS Attacks on LTE and LoRaWAN Protocols in the NS-3 Network Simulator;transaction-Oriented Approach to the Design of Information systems Based on Formal Grammar;frequency-Domain Generalized Phase Transform Method in Pipeline Leaks Locating;inverse Problem Regularization of Parametric Identification of the Particle Temperature Distribution of Gas-thermal Flow with Optimization of Its Solution;application of the Heterogeneous Multiscale Finite Element Method for Modelling the Compressibility of Porous Media.

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FP-BMAC: Efficient Approximate Floating-Point Bit-Parallel MAC Processor using IMC 37

FP-BMAC: Efficient Approximate Floating-Point Bit-Parallel M...

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37th international conference on VLSI Design (VLSID) / 23rd international conference on Embedded systems (ES)

作者： Gajawada, Saketh Gupta, Aryan Prasad, Kailash Mekie, Joycee IIIT Bangalore Bangalore Karnataka India IIT Gandhinagar Gandhinagar India

ISBN: (纸本)9798350384406

In-memory computing (IMC) has emerged as a promising solution to address the energy and performance bottlenecks of traditional von Neumann architectures. this paper presents FP-BMAC, a novel bit-parallel in-memory computing architecture that efficiently handles floating-point multiply-and-accumulate (MAC) operations with reconfigurable FP precision. the architecture employs a novel approach to compute mantissa bits using an approximate right-shift multiplication method, which ensures alignment of output mantissa length with the input and enhances storage efficiency. the architecture effectively reduces computation delays and improves overall performance by incorporating BL Separator and BL Boosting circuits. the bit-parallel IMC macro achieves remarkable energy efficiency improvements, achieving a normalized throughput of 12.19 GFLOPS/Kb for FP Multiplication and 16.94 TFLOPS/W for MAC Operation at 1.15 GHz in CMOS 28nm technology.

关键词： In-Memory computing Process-In-Memory Approximate computing Floating Point

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FP-ATM: A Flexible Floating Point NOR Adder Tree Macro for In-Memory computing 37

FP-ATM: A Flexible Floating Point NOR Adder Tree Macro for I...

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37th international conference on VLSI Design (VLSID) / 23rd international conference on Embedded systems (ES)

作者： Attuluri, Yathin Kumar Chudasama, Ruchit Prasad, Kailash Mekie, Joycee IIIT Bangalore Bangalore Karnataka India IIT Gandhinagar Gandhinagar India

ISBN: (纸本)9798350384406

In-Memory computing (IMC) has emerged as a promising approach to address the von Neumann bottleneck in deep learning applications. this work proposes FP-ATM, a 6T SRAM-based all-digital design for multiply-accumulate (MAC) operations, featuring a flexible NOR Adder Tree for In-Memory computing. the proposed macro is data-aware and can support input activations and weights for INT8 and BF16 number formats in a convolutional neural network. Using multiple macros in different configurations can support neural networks with different topologies. the proposed macro is based on bit-serial multiplication and parallel adder trees. this architecture can achieve massively parallel MAC operations with high energy efficiency and throughput. the proposed macro achieves a peak energy efficiency of 267.7 TFLOPS/W at 0.65V, 8.5 times the state-of-the-art work. the maximum frequency is 1.67 GHz and achieves throughput of 2.67 GFLOPS/Kb at a voltage of 0.9V.

关键词： Digital In-Memory computing Floating Point NOR Adder Tree Macro

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OEDASA: Optimization Enabled Error-Diluted Approximate Systolic Array Design for an Image Processing Application 37

OEDASA: Optimization Enabled Error-Diluted Approximate Systo...

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37th international conference on VLSI Design (VLSID) / 23rd international conference on Embedded systems (ES)

作者： Devi, Dantu Nandini Kumar, Gandi Ajay Gowda, Bindu G. Rao, Madhav IIIT Bangalore Bangalore Karnataka India

ISBN: (纸本)9798350384406

Systolic Array (SA) architecture is a hardware accelerator for running Artificial Intelligence (AI) workloads. Although approximate computing offers hardware and performance benefits, it often sacrifices accuracy, limiting its application to error-resilient tasks. Many inexact multipliers in SA exhibit one-sided Error Distribution (ErD), resulting in significant accumulated errors. Approximate computing proves valuable in error-resilient image processing applications, fostering research into various approximation techniques for enhanced hardware performance. this paper explores SA architecture with different configurations of approximate multipliers (AMs) featuring distinct ErDs. It employs a meta-heuristic optimization algorithm, Particle Swarm Optimization (PSO), for image smoothing tasks. the study delves into trade-offs between hardware acceleration and accuracy, offering insights for advancing approximate computing in SA-based AI workloads. the PSO-evolved SA configuration showcases a 3.05% performance improvement, 10.63% silicon footprint reduction, and 10.32% power savings compared to the exact SA. the PSO-derived SA structure also offers notable hardware gains when compared with other state-of-theart (SOTA) benchmark designs. Additionally, it demonstrates a better Structural Similarity Index (SSIM) compared to SA with one-sided error-distributed AMs. the proposed spatially optimized SAs with AMs of different ErDs represent a step towards reliable hardware design and establishing a nearly exact AI accelerator system. All design files and results are shared openly with the research and design community for easy adoption and further exploration.

关键词： Systolic Array Convolution Approximate computing Image Processing Particle Swarm Optimisation (PSO)

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Vigil: A RISC-V SoC architecture for 2-fold Hybrid CNN-kNN based Fall Detector Implementation on FPGA 37

Vigil: A RISC-V SoC Architecture for 2-fold Hybrid CNN-kNN b...

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37th international conference on VLSI Design (VLSID) / 23rd international conference on Embedded systems (ES)

作者： Bhattacharyya, Tamonash Ghosal, Prasun Sonam Deb, Sujay Indian Inst Engn Sci & Technol Dept IT Sibpur India Indraprastha Inst Informat Technol Dept ECE Delhi India

ISBN: (纸本)9798350384406

Passive, round-the-clock Health Monitoring at scale is necessary in modern society with the potential to detect adversarial health events in real-time environments. Accidental Falls constitute one of the leading causes of injuries in the elderly. this study focuses on low latency, power-efficient implementation of an Accidental Fall Detection System in dynamic environments from Accelerometer and PPG sensor data, using a hybrid CNN-kNN estimator on a RISC-V-based SoC platform. RISC-V is an open, base-plus-extension ISA suited ideally for custom SoC designs that can be configured to include the absolute necessity for an application, minimizing costs and memory usage. the hybrid model comprises a probabilistic Convolution Neural Network in conjunction with the nearest neighbor classifier for the final layer classification. Our SoC design thus focuses on an efficient Hardware (FPGA) Implementation of the custom probabilistic CNN (pCNN) architecture for motion and vital signal analysis, along with a kNN model for the final fall estimation.

关键词： RISC-V Internet-of-things (IoT) Hardware-Software Co-design Edge computing FPGA Fall Detection Assistive Technologies Hardware for AI pCNN CNN-kNN PolarFire SoC

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GesturePrint: Enabling User Identification for mmWave-based Gesture Recognition systems 44

GesturePrint: Enabling User Identification for mmWave-based ...

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44th IEEE international conference on Distributed computing systems (ICDCS)

作者： Xu, Lilin Wang, Keyi Gu, Chaojie Guo, Xiuzhen He, Shibo Chen, Jiming Zhejiang Univ Hangzhou Peoples R China Univ Calif San Diego La Jolla CA 92093 USA

ISBN: (纸本)9798350386066;9798350386059

the millimeter-wave (mmWave) radar has been exploited for gesture recognition. However, existing mmWave-based gesture recognition methods cannot identify different users, which is important for ubiquitous gesture interaction in many applications. In this paper, we propose GesturePrint, which is the first to achieve gesture recognition and gesture-based user identification using a commodity mmWave radar sensor. GesturePrint features an effective pipeline that enables the gesture recognition system to identify users at a minor additional cost. By introducing an efficient signal preprocessing stage and a network architecture GesIDNet, which employs an attention-based multi-level feature fusion mechanism, GesturePrint effectively extracts unique gesture features for gesture recognition and personalized motion pattern features for user identification. We implement GesturePrint and collect data from 17 participants performing 15 gestures in a meeting room and an office, respectively. GesturePrint achieves a gesture recognition accuracy (GRA) of 98.87% with a user identification accuracy (UIA) of 99.78% in the meeting room, and 98.22% GRA with 99.26% UIA in the office. Extensive experiments on three public datasets and a new gesture dataset show GesturePrint's superior performance in enabling effective user identification for gesture recognition systems.

关键词： Gesture recognition Millimeter-wave radar RF sensing User identification

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computing services oriented evolutionary architecture and key technologies of electric power communication network 24

Computing services oriented evolutionary architecture and ke...

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24th IEEE international conference on Communication Technology, ICCT 2024

作者： Zhang, Xiangyi Zhao, Xing Gao, Xiaofang Zhao, Hanyu Tang, Jia Guo, Xiaoxi Chen, Yanyu Zhao, Junfeng State Grid Information & Communication Beijing China Beijing China

ISBN: (纸本)9798350363760

With the deepening of the digital transformation of power systems, new service scenarios such as computing power access and interconnection are continuously developing. the electric power communication network urgently needs to evolve to comprehensively carry the existing services and new computing services. this paper analyzes the typical service scenarios and performance characteristics of new power systems against the development of computing services, summarizes the evolution demands faced by the electric power communication network. In response to the demand for comprehensive carrying of multiple services, the paper proposes a computing application oriented overall evolutionary architecture for the power communication network, and proposes key technologies such as all-optical interconnection based on OTN/OSU, multi-dimensional perception of computing and network, deterministic bearing, and intelligent collaborative operation and maintenance of computing and network. this paper can provide solid strategic suggestions for the future design and technological evolution of the electric power communication network oriented to computing services. © 2024 IEEE.

关键词： computing power

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Input Distribution Aware Library of Approximate Adders Based on Memristor-Aided Logic 37

Input Distribution Aware Library of Approximate Adders Based...

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37th international conference on VLSI Design (VLSID) / 23rd international conference on Embedded systems (ES)

作者： Jha, Chandan Kumar Ahmadi-Pour, Sallar Drechsler, Rolf Univ Bremen Inst Comp Sci Bremen Germany DFKI GmbH German Res Ctr Artificial Intelligence Bremen Germany

ISBN: (纸本)9798350384406

Memristor-aided logic (MAGIC) is one of the most popular design styles for implementing Logic-in-Memory (LiM) using memristors. MAGIC-based LiM has been shown to be useful for high throughput applications, as the same design can be mapped to multiple rows of a crossbar. the computations can be performed simultaneously on all these rows on different inputs to achieve high throughput. In recent years, approximate circuits have been extensively explored to obtain benefits in power, performance, and area for traditional CMOS designs. While these approximate circuits produce erroneous outputs, several applications can produce an acceptable quality output even with these approximations. In this work, we propose approximate circuits for MAGIC-based LiM. We have used the Ripple Carry Adder (RCA) architecture and introduced functional approximation to generate the approximate RCAs. We obtained the mapping of these approximate RCAs on the memristor crossbar using the SIMPLER MAGIC tool. We generated the Pareto-optimal designs using Gate Count and Total Cycles as design metrics against Mean Square Error and Mean Absolute Error as error metrics. We generated separate Pareto-optimal designs for three different input data distributions namely uniform, exponential, and normal data distributions.

关键词： Approximate computing memristor-aided logic logic-in-memory pareto-optimal input distribution adders

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