the proceedings contain 130 papers. the topics discussed include: FPGA implementation of low-power split-radix FFT processors;a combination of multi-edge coding and independent coding lines for time-to-digital convers...
ISBN:
(纸本)9783000446450
the proceedings contain 130 papers. the topics discussed include: FPGA implementation of low-power split-radix FFT processors;a combination of multi-edge coding and independent coding lines for time-to-digital conversion;using high-level knowledge to enhance data channels in FPGA streaming systems;hardware conversion of neural networks simulation models for neural processing accelerator implemented as FPGA-based SoC;efficient multi-standard cognitive radios on FPGAs;biomedical image processing and reconstruction with dataflow computing on FPGAs;improve defect tolerance in a cluster of a SRAM-based mesh of cluster FPGA using hardware redundancy;efficient implementation of a single-precision floating-point arithmetic unit on FPGA;a fast and scalable FPGA damage diagnostic service for R3TOS using BIST cloning technique;a soft-core processor for finite field arithmetic with a variable word size accelerator;and ultrasmall: the smallest MIPS soft processor.
In this paper a novel, low-latency family of high-radix Parallel Prefix Network adders and modular adders has been proposed. this family efficiently takes advantage of fast carry chains of modern FPGAs. the implementa...
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In this paper, we propose a design support tool set for asynchronous circuits with bundled-data implementation to implement them on commercial FPGAs easily considering a latency constraint. the design support tool set...
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fieldprogrammable Gate Arrays (FPGAs) are an ideal platform for building systems with custom hardware accelerators, however managing these systems is still a major challenge. the OpenCL standard has become accepted a...
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this paper presents a novel methodology for generating and compressing configuration bitstreams for modules that can be executed at different positions of an FPGA. the presented methodology for bitstream generation an...
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the PCIe attachment of FPGA accelerators within host workstations is convenient and offers a high-performance direct integration. FPGA-boards designed and equipped as PCIe extension cards are available off-the-shelf. ...
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In classical FPGA, LUTs and DFFs are pre-packed into BLEs and then BLEs are grouped into logic blocks. We propose a novel logic block architecture with fast combinational paths between LUTs, called pattern-based logic...
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Many network services including intrusion detection and recommendation provide their services by analyzing information acquired from network transactions. A careful analysis of these data can reveal valuable informati...
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Optical flow estimation of image sequences is one of the key elements for motion detection. However, processing the optical flow in real-time is still an open task due to its computationally expensive nature. In this ...
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Increasing chip sizes and better programming tools have made it possible to increase the boundaries of application acceleration with FPGAs. Two applications, localization microscopy and electron tomography, are presen...
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