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Heterogeneous dataflow architectures for FPGA-based sparse LU factorization

Heterogeneous dataflow architectures for FPGA-based sparse L...

引用

international conference on field programmable logic and applications

作者： Siddhartha Nachiket Kapre Nanyang Technological University Singapore Singapore SG

FPGA-based token dataflow architectures with heterogeneous computation and communication subsystems can accelerate hard-to-parallelize, irregular computations in sparse LU factorization. We combine software pre-processing and architecture customization to fully expose and exploit the underlying heterogeneity in the factorization algorithm. We perform a one-time pre-processing of the sparse matrices in software to generate dataflow graphs that capture raw parallelism in the computation through substitution and reassociation transformations. We customize the dataflow architecture by picking the right mixture of addition and multiplication processing elements to match the observed balance in the dataflow graphs. Additionally, we modify the network-on-chip to route certain critical dependencies on a separate, faster communication channel while relegating less-critical traffic to the existing channels. Using our techniques, we show how to achieve speedups of up to 37% over existing state-of-the-art FPGA-based sparse LU factorization systems that can already run 3-4× faster than CPU-based sparse LU solvers using the same hardware constraints.

关键词： Benchmark testing Computer architecture field programmable gate arrays Sparse matrices Hardware Parallel processing Optimization

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Efficient implementation of a single-precision floating-point arithmetic unit on FPGA

Efficient implementation of a single-precision floating-poin...

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international conference on field programmable logic and applications

作者： Wilson José Ana Rita Silva Horácio Neto Mário Véstias INESC-ID Universidade de Lisboa Portuzal INESC-ID Instituto Superior de Engenharia de Lisboa IPL Portugal

this paper presents a single precision floating point arithmetic unit with support for multiplication, addition, fused multiply-add, reciprocal, square-root and inverse square-root with high-performance and low resource usage. the design uses a piecewise 2 nd order polynomial approximation to implement reciprocal, square-root and inverse square-root. the unit can be configured with any number of operations and is capable to calculate any function with a throughput of one operation per cycle. the floating-point multiplier of the unit is also used to implement the polynomial approximation and the fused multiply-add operation. We have compared our implementation with other state-of-the-art proposals, including the Xilinx Core-Gen operators, and conclude that the approach has a high relative performance/area efficiency.

关键词： Digital signal processing field programmable gate arrays Polynomials Adders Function approximation Table lookup

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Incremental distributed trigger insertion for efficient FPGA debug

Incremental distributed trigger insertion for efficient FPGA...

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international conference on field programmable logic and applications

作者： Fatemeh Eslami Steven J.E. Wilton The University of British Columbia Faculty of Medicine Vancouver BC CA

FPGA-based prototyping enables evaluating complex designs directly in hardware, at speeds orders of magnitude faster than simulation. However, this approach suffers from the lack of observability during debugging. To enhance observability, designers insert debug instrumentation; trace buffers are used to record a small subset of data. Since these buffers have limited capacity, trigger circuits are required to start and/or stop recording based on the values of selected signals in the circuit. Although it is possible to insert trigger circuits at compile time, changing the trigger behaviour requires re-compiling the design, increasing the cost of each debug iteration. In this paper, we propose inserting trigger circuits at run-time by distributing trigger logic over spare resources of a fully placed-and-routed design such that its mapping is completely preserved. We also propose CAD optimizations which improve routability of the trigger circuitry, and minimize the impact on circuit delay. We find that using our techniques to implement the trigger logic can be an order of magnitude faster than a full recompilation.

关键词： Routing field programmable gate arrays Delays Benchmark testing Trigger circuits Design automation Random access memory

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Transparent insertion of latency-oblivious logic onto FPGAs

Transparent insertion of latency-oblivious logic onto FPGAs

引用

international conference on field programmable logic and applications

作者： Eddie Hung Tim Todman Wayne Luk Imperial College London London London GB

We present an approach for inserting latency-oblivious functionality into pre-existing FPGA circuits transparently. To ensure transparency - that such modifications do not affect the design's maximum clock frequency - we insert any additional logic post place-and-route, using only the spare resources that were not consumed by the pre-existing circuit. the typical challenge with adding new functionality into existing circuits incrementally is that spare FPGA resources to host this functionality must be located close to the input signals that it requires, in order to minimise the impact of routing delays. In congested designs, however, such co-location is often not possible. We overcome this challenge by using flow techniques to pipeline and route signals from where they originate, potentially in a region of high resource congestion, into a region of low congestion capable of hosting new circuitry, at the expense of latency. We demonstrate and evaluate our approach by augmenting realistic designs with self-monitoring circuitry, which is not sensitive to latency. We report results on circuits operating over 200MHz and show that our insertions have no impact on timing, are 2-4 times faster than compile-time insertion, and incur only a small power overhead.

关键词： Routing Pipeline processing field programmable gate arrays Registers Clocks Delays Table lookup

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Towards dark silicon era in FPGAs using complementary hard logic design

Towards dark silicon era in FPGAs using complementary hard l...

引用

international conference on field programmable logic and applications

作者： Ali Ahari Behnam Khaleghi Zahra Ebrahimi Hossein Asadi Mehdi B. Tahoori Sharif University of Technology Tehran Tehran IR Karlsruher Institut fur Technologie Karlsruhe Baden-WÃ¼rttemberg DE

While the transistor density continues to grow exponentially in field-programmable Gate Arrays (FPGAs), the increased leakage current of CMOS transistors act as a power wall for the aggressive integration of transistors in a single die. One recently trend to alleviate the power wall in FPGAs is to turn off inactive regions of the silicon die, referred to as dark silicon. this paper presents a reconfigurable architecture to enable effective fine-grained power gating of unused logic Blocks (LBs) in FPGAs. In the proposed architecture, the traditional soft logic is replaced with Mega Cells (MCs), each consists of a set of complementary Generic Reconfigurable Hard logic (GRHL) and a conventional Look-Up Table (LUT). Both GRHL cells and LUTs can be power gated and turned off by controlling configuration bits. In the proposed MC, only one cell is active and the others are turned off. Experimental results on MCNC benchmark suite reveal that the proposed architecture reduces the critical path delay, power, and Power Delay Product (PDP) of LBs up to 5.3%, 30.4%, and 28.8% as compared to the equivalent LUT-based architecture.

关键词： Table lookup logic gates Silicon Delays Benchmark testing Iron

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High-level synthesis-based design methodology for Dynamic Power-Gated FPGAs

High-level synthesis-based design methodology for Dynamic Po...

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international conference on field programmable logic and applications

作者： Rehan Ahmed Assem A. M. Bsoul Steven J. E. Wilton Peter Hallschmid Richard Klukas The University of British Columbia Canada Blackcomb Design Automation Canada

Static leakage power consumption is critical in modern FPGAs for many applications. Dynamic Power-Gating (DPG), in which parts of the FPGA in-use logic blocks are powered-down at run-time, is a promising technique to reduce the static power. Adoption of such emerging DPG enabled FPGA architectures remains challenging as the current tool-chains to program the FPGA does not support this type of power-gating. Moreover, manually identifying profitable power-gating opportunities in an application requires significant design expertise and is time consuming. In this paper, we propose a high-level synthesis-based design framework that exploits the dynamic power-gating feature of the FPGAs to minimize the static power dissipation. We use this framework on a set of CHStone benchmark suite and demonstrate that power-gating opportunities for hardware accelerators can be identified in an automatic way. Results show that up to 96% reduction in static energy is achieved for individual accelerators using dynamic power-gating technique.

关键词： field programmable gate arrays Benchmark testing Acceleration Design automation Hardware Computer architecture Fabrics

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FPGA architecture support for heterogeneous, relocatable partial bitstreams

FPGA architecture support for heterogeneous, relocatable par...

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international conference on field programmable logic and applications

作者： Christophe Huriaux Olivier Sentieys Russell Tessier Universite de Rennes 1 Rennes Bretagne FR IRISA Rennes Bretagne FR University of Massachusetts Amherst Amherst MA US

the use of partial dynamic reconfiguration in FPGA-based systems has grown in recent years as the spectrum of applications which use this feature has increased. For these systems, it is desirable to create a series of partial bitstreams which represent tasks which can be located in multiple regions in the FPGA fabric. While the transferal of homogeneous collections of lookup-table based logic blocks from region to region has been shown to be relatively straightforward, it is more difficult to transfer partial bitstreams which contain fixed-function resources, such as block RAMs and DSP blocks. In this paper we consider FPGA architecture enhancements which allow for the migration of partial bitstreams including fixed-function resources from region to region even if these resources are not located in the same position in each region. Our approach does not require significant, time-consuming place-and-route during the migration process. We quantify the cost of inserting additional routing resources into the FPGA architecture to allow for easy migration of heterogeneous, fixed-function resources. Our experiments show that this flexibility can be added for a relatively low overhead and performance penalty.

关键词： field programmable gate arrays Routing Fabrics Arrays Switches Wires

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Aging effects in FPGAs: an experimental analysis

Aging effects in FPGAs: an experimental analysis

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international conference on field programmable logic and applications

作者： Abdulazim Amouri Florent Bruguier Saman Kiamehr Pascal Benoit Lionel Torres Mehdi Tahoori Institute of Computer Engineering Karlsruhe Institute of Technology (KIT) Karlsruhe Germany LIRMM CNRS - University of Montpellier 2 Montpellier France

Modern field programmable Gate Arrays (FPGAs) are built using the most advanced technology nodes to meet performance and power demands. this makes them susceptible to various reliability challenges at nano-scale, and in particular to transistor aging. In this paper, an experimental analysis is made to identify the main parameters and phenomena influencing the performance degradation of FPGAs. For that purpose, a set of controlled ring-oscillator-based sensors with different frequencies and tunable activity control are implemented on a Spartan-6 FPGA. thus, the internal switching activities (SAs) and signal probabilities (SPs) of the sensors can be varied. We performed accelerated-lifetime conditions using elevated temperatures and voltages in a controlled setting to stress the FPGA. A novel monitoring method based on measuring the electromagnetic emissions of the FPGA is used to accurately monitor the performance of the sensors before and after the stress. the experiments reveal the extent of performance degradations, the impact of SPs and SAs, and the relative impacts of BTI and HCI aging factors.

关键词： field programmable gate arrays Aging Stress Degradation Transistors Temperature sensors

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A survey of open source processors for FPGAs

A survey of open source processors for FPGAs

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international conference on field programmable logic and applications

作者： Rui Jia Colin Yu Lin Zhenhong Guo Rui Chen Fei Wang Tongqiang Gao Haigang Yang University of Chinese Academy of Sciences Beijing China System on Programmable Chip Research Department Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781479933624

FPGA-based SoCs have been gaining great favors among traditional applications and expanding the application domains to some new areas. Reusing and sharing components is an attractive and pratical methodology for system designers to reduce the design complexity of the SoC architectures. Open source hardware has become an effective method of improving the design productivity. As the core functional component, processors affects the performance of SoC systems. this paper investigates existing open source processors, and gives an overview. From the points of usability and stability, the main features of open source processors are summarized. Following these features, some open source processors with high usability and stability are selected. these open source processors and existing vendor-provided soft processors are implemented on Stratix V and Virtex-7 FPGAs using corresponding EDA tools, Quart us n and ISE. the implementation results are compared and discussed.

关键词： field programmable gate arrays Java Registers Licenses Multicore processing Reduced instruction set computing

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Run-time power gating in hybrid ARM-FPGA devices

Run-time power gating in hybrid ARM-FPGA devices

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international conference on field programmable logic and applications

作者： Mohammad Hosseinabady Jose Luis Nunez-Yanez Department of Electrical and Electronic Engineering University of Bristol UK

Energy proportional computing (EPC) enables the allocation of energy to tasks depending on computational demands. Computing at full speed and then dynamically turning off modules when they are not required for a period of time can be used to obtain EPC and it is an alternative to voltage scaling techniques in which the computation is slowed down. this paper investigates the viability of physical power gating FPGA devices that incorporate a hardened processor in a different power domain. the run-time power gating approach is applied to Xilinx ZYNQ devices that incorporate a hardened Cortex A9 multi-processor. the paper demonstrates that power down followed by a full reconfiguration can be controlled by the embedded processor autonomously. the results show that the minimum time that the FPGA fabric must remain in power-off state for the technique to be energy efficient is in the order of milliseconds and up to 96% power reduction occurs when the fabric voltage is lowered below critical level. these results take into account the overheads of controlling the programmable voltage regulators interfaced to the FPGA and the overhead of the reconfiguration needed when the device must be returned to the active state.

关键词： field programmable gate arrays Power demand Turning Transistors Switching circuits Software Clocks

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