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Balancing WDDL dual-rail logic in a tree-based FPGA to enhance physical security

Balancing WDDL dual-rail logic in a tree-based FPGA to enhan...

引用

international conference on field programmable logic and applications

作者： Emna Amouri Shivam Bhasin Yves Mathieu Tarik Graba Jean-Luc Danger Habib Mehrez CNRS LTCI (UMR 5141) Departement COMELEC Institut TELECOM/TELECOM ParisTech. Paris France LIP6 Universite Pierre et Marie Curie 4 Paris France

the Tree-based FPGA offers better density and timing determinism than traditional mesh-based FPGA. Moreover, thanks to its multilevel structure, it offers greater easiness to balance dual signals in terms of routing resources number. In this paper, we study the use of the Wave Dynamic Differential logic (WDDL) on a custom tree-based FPGA of 2048 cells. the WDDL technique offers an effective way to withstand Differential Power Attacks (DPA). However, the effectiveness of this countermeasure is guaranteed provided a symmetry is maintained between the routing of both the direct and complementary paths, which is very hard to achieve in FPGA. thus, balancing aware Computer-Aided Design (CAD) tools must be developed. In this work, we propose first adjacent placement and balancing-aware routing techniques for tree-based FPGA to counter the routing unbalance. then side channel analyses are performed on FPGA circuit implementing PRESENT crypto-processor. Experimental results show that the balancing methods enhance the design security against side channel attacks.

关键词： Routing field programmable gate arrays Delays Cryptography Switches

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Criticality-aware scrubbing mechanism for SRAM-based FPGAs

Criticality-aware scrubbing mechanism for SRAM-based FPGAs

引用

international conference on field programmable logic and applications

作者： Rui Santos Shyamsundar Venkataraman Anup Das Akash Kumar Department of Electrical & Computer Engineering National University of Singapore

Scrubbing has been considered as an effective mechanism to provide fault-tolerance in Static-RAM (SRAM)-based field programmable Gate Arrays (FPGAs). However, the current scrubbing techniques execute without considering the criticality and timing of the user tasks implemented in the FPGA. they often do not execute the scrubbing process in the right instant, which minimizes the probability of each task being executed without transient faults. Moreover, these current solutions are not adapted to the tasks' fault-tolerance requirements, since they may not properly protect the most critical tasks in the system. However, if they do it, they waste resources with the less critical tasks. In this paper, a new scrubbing mechanism is proposed. this new approach adapts the scrubbing mechanism to the tasks' execution, by a proper scheduling and according to their criticality. A proposed heuristic finds a feasible scrubbing schedule for each hardware task. Firstly, the minimum scrubbing periods are computed according to the criticality of each implemented hardware task. Secondly, a proper scrubbing schedule following the EDL (Earliest Deadline as Late as possible) algorithm is found, maximizing the reliability of the system. the experimental results show up to 79% improvements on the system reliability, achieved without wasting scrubbing resources.

关键词： field programmable gate arrays Hardware Schedules Equations Fault tolerance Fault tolerant systems

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Accelerate NDN name lookup using FPGA: Challenges and a scalable approach

Accelerate NDN name lookup using FPGA: Challenges and a scal...

引用

international conference on field programmable logic and applications

作者： Yanbiao Li Dafang Zhang Xian Yu Wei Liang Jing Long Hong Qiao College of Computer Science and Electronic Engineering Hunan University Changsha China College of Computer Science and Engineering Hunan University of Science and Technology Xiangtan China

Recently, Graphic Processing Units (GPUs) have been shown to be of value in supporting wire-speed name lookup in Named Data Networking (NDN). However, due to the computing model on GPU, the lookup latency is not so encouraging. In this paper, we shift the focus from GPU to field-programmable Gate Arrays (FPGA). We highlight three key challenges in accelerating name lookup using FPGA, and then present a scalable approach to address them. In our approach, a hierarchical and compact data structure is proposed to represent the name trie, which achieves not only effective pipeline mapping but also high memory efficiency. Further, it is finally implemented as a linear pipeline on the FPGA platform, enabling both fast lookup speed and low lookup latency. the experimental results show that our approach gains a reduction of memory cost over 90% compared with the referred GPU-based solution. Besides, the lookup throughput of our approach is almost 2.4 times higher, and the latency is up to 3 orders of magnitude lower.

关键词： Pipelines field programmable gate arrays Random access memory Graphics processing units throughput Silicon Acceleration

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An FPGA-based image connected component labeller

An FPGA-based image connected component labeller

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13th international conference on field-programmable logic and applications (fpl 2003)

作者： Benkrid, K Sukhsawas, S Crookes, D Benkrid, A Queens Univ Belfast Sch Comp Sci Belfast BT7 1NN Antrim North Ireland

ISBN: (纸本)3540408223

this paper describes an FPGA implementation of a Connected Component Labelling algorithm (CCL), developed at Queen's University Belfast. the algorithm iteratively scans the input image, performing a non-zero maximum neighbourhood operation. It has been coded in Handel C language and targeted Celoxica RC1000-PP PCI board. the whole design was fully implemented and tested on real hardware in less than 24 man-hour. It uses a Virtex-E FPGA and two banks of off-chip memory. For 1024x1024 input images, the whole circuit consumes 583 FPGA slices and 5 Block RAMs and can run at 72 MHz, leading to a 68 pass/sec performance. the FPGA implementation outperforms, easily, an equivalent software implementation running on a 1.6 GHz Pentium-IV PC. A 10-fold speed up has been realised in many instances.

关键词： field programmable gate arrays (FPGA)

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Simplification and hardware implementation of the feature descriptor vector calculation in the SIFT algorithm

Simplification and hardware implementation of the feature de...

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international conference on field programmable logic and applications

作者： P. Leyva G. Doménech-Asensi J. Garrigós J. Illade-Quinteiro V. M. Brea P. López D. Cabello Dpto. de Electrónica Tec. de Computadoras y Proyectos Universidad Politécnica de Cartagena Cartagena Spain Centro de Inv. en Tecnoloxías da Información (CITIUS) University of Santiago de Compostela Santiago de Compostela Spain

this paper proposes a hardware implementation to speed up the calculation of the feature descriptor vector in the Scale-Invariant Feature Transform (SIFT) algorithm. the proposed architecture, which improves conventional solutions based on embedded processors or other hardware/software co-designs, computes a feature descriptor vector of 27 elements from a keypoint neighborhood of 15×15 pixels. this process comprises several steps, including complex operations such as vector normalization operations. the paper compares two different implementations: one being time-optimized and the other memory-optimized. Both approaches require 649 and 874 clock cycles respectively for a single feature vector calculation (6.49 μs and 8.74 μs for a 100 MHz FPGA).

关键词： Vectors Histograms Hardware Topology Feature extraction Computer architecture field programmable gate arrays

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An efficient and flexible host-FPGA PCIe communication library

An efficient and flexible host-FPGA PCIe communication libra...

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international conference on field programmable logic and applications

作者： Jian Gong Tao Wang Jiahua Chen Haoyang Wu Fan Ye Songwu Lu Jason Cong Peking University Beijing Beijing CN

A high-performance interconnection between a host processor and FPGA accelerators is in much demand. Among various interconnection methods, a PCIe bus is an attractive choice for loosely coupled accelerators. Because there is no standard host-FPGA communication library, FPGA developers have to write significant amounts of PCIe related code at both the FPGA side and the host processor side. A high-performance host-FPGA PCIe communication library holds the key to broadening the use of FPGA accelerators. In this paper we target efficiency and flexibility as two important features in such a library. We discuss the challenges in providing these features, and present our solution to these challenges. We propose EPEE, an efficient and flexible host-FPGA PCIe communication library and describe its design. We implemented EPEE in various generations of Xilinx FPGAs with up to 26.24 Gbps half-duplex and 43.02 Gbps full-duplex aggregate throughput in the PCIe Gen2 X8 mode; these are at the best utilization levels that a host-FPGA PCIe library can achieve. the EPEE library has been integrated into four different FPGA applications with different data usage patterns in various institutes.

关键词： field programmable gate arrays Libraries Software Hardware throughput IP networks Registers

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High throughput channel tracking for JTRS wireless channel emulation

High throughput channel tracking for JTRS wireless channel e...

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international conference on field programmable logic and applications

作者： Dajung Lee Janarbek Matai Brad Weals Ryan Kastner Electrical and Computer Engineering Computer Science and Engineering University of California San Diego Toyon Research Corporation

Testing and verifying wireless systems in a real world environments is a challenging but an important problem. this is particular true for the Joint Tactical Radio System (JTRS) where the modulation techniques are optimized towards environments that are difficult to reproduce (e.g., ship to plane, plane to satellite communications). Such cases necessitate a wireless channel emulator to facilitate testing in the laboratory as the protocols are being developed. Furthermore, the increasing complexity of communications protocols and highly variable network scenarios force the channel emulator to support an accurate and complicated channel model that can scale to handle a large number of radios that operate across a wide frequency spectrum. We developed a unique channel impairment emulator prototype to meet these requirements. It maximizes the scalability and performance, operating in a frequency range of 2 MHz to 2 GHz. Moreover, our emulator design accommodates radio operation that use unknown frequency hopping techniques, which is increasingly common in JTRS systems. this key feature to this system is a high throughput channel tracker module that handles high bandwidth intermediate frequency (IF) signals while providing the scalability to handle a large number of channels.

关键词： throughput Wireless communication field programmable gate arrays Optimization Hardware Clocks Radio frequency

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Patra: Parallel tree-reweighted message passing architecture

Patra: Parallel tree-reweighted message passing architecture

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international conference on field programmable logic and applications

作者： Wenlai Zhao Haohuan Fu Guangwen Yang Wayne Luk Ministry of Education Key Laboratory for Earth System Modeling Tsinghua University Tsinghua National Laboratory for Information Science and Technology (TNList) Department of Computing Imperial College London

Maximum a posteriori probability inference algorithms for Markov Random field are widely used in many applications, such as computer vision and machine learning. Sequential tree-reweighted message passing (TRW-S) is an inference algorithm which shows good quality in finding optimal solutions. However, the performance of TRW-S in software cannot meet the requirements of many real-time applications, due to the sequential scheme and the high memory, bandwidth and computational costs. this paper proposes Patra, a novel parallel tree-reweighted message passing architecture, which involves a fully pipelined design targeting FPGA technology. We build a hybrid CPU/FPGA system to test the performance of Patra for stereo matching. Experimental results show that Patra provides about 100 times faster than a software implementation of TRW-S, and 12 times faster than a GPU-based message passing algorithm. Compared with an existing design in four FPGAs, we can achieve 2 times speedup in a single FPGA. Moreover, Patra can work at video rate in many cases, such as a rate of 167 frame/sec for a standard stereo matching test case, which makes it promising for many real-time applications.

关键词： field programmable gate arrays Message passing Algorithm design and analysis Bandwidth Random access memory Accuracy Vectors

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Tile-based bottom-up compilation of custom mesh-of-functional-units FPGA overlays

Tile-based bottom-up compilation of custom mesh-of-functiona...

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international conference on field programmable logic and applications

作者： Davor Capalija Tarek S. Abdelrahman Department of Electrical and Computer Engineering University of Toronto Toronto ON Canada

Mesh-of-functional-units (mesh-of-FUs) overlays can deliver high-performance because they expose the massively parallel FPGA fabric and have the ability to be customized for different applications. However, a key challenge is how to quickly compile a number of custom mesh-of-FUs overlays to FPGA fabric such that they achieve high f MAX and scale to large mesh sizes. We propose a tile-based bottom-up CAD flow that utilizes the hierarchical physical design techniques of partitioning and floorplanning. Our flow partitions the overlay circuit into tiles, groups of adjacent overlay cells, and then compiles the tiles to a rectangular coarse-grain floorplan. Independent compilation of tiles is made possible by inserting complementary elastic buffers on inter-tile paths to ensure that these paths are not a bottleneck for f MAX . As a result, an overlay can be formed by only “stitching” a set of pre-compiled *** show that compared to the flat flow, our bottom-up flow results in higher f MAX that degrades little with increasing overlay size. Further, our flow can generate a library of pre-compiled tiles that can be reused - it can stitch a set of library tiles into a new overlay in only 35 minutes. It also allows a divide-and-conquer overlay compilation flow by compiling its tiles in parallel on multiple machines.

关键词： field programmable gate arrays Design automation Registers Libraries Ports (Computers) Layout Digital signal processing

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Privacy preserving large scale DNA read-mapping in MapReduce framework using FPGAs

Privacy preserving large scale DNA read-mapping in MapReduce...

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international conference on field programmable logic and applications

作者： Lei Xu Hanyee Kim Xi Wang Weidong Shi Taeweon Suh University of Houston United States Korea University Republic of Korea

Read-mapping, i.e., finding certain patterns in a long DNA sequence, is an important operation for molecular biology. It is widely used in a variety of biological analyses including SNP discovery, genotyping and personal genomics. As next-generation DNA sequencing machines are generating an enormous amount of sequence data, it is a good choice to implement the read-mapping algorithm in the MapReduce framework and outsource the computation to the cloud. Data privacy becomes a big concern in this situation as DNA sequences are very sensitive. In response, encryption may be used to protect the data. However, it is very difficult for the cloud to process cipher texts. In the MapReduce framework, even if values (data to be processed) may be protected by encryption, keys cannot be encrypted using sematic secure encryption schemes as it will affect the MapReduce scheduling mechanism. But if no protection is utilized, attackers may extract useful information from unprotected keys. We propose a solution that can securely outsource read-mapping computations in the MapReduce framework by leveraging inherent tamper resistant properties of FPGAs. We also provide a method to protect the keys generated in this process. We implement our solution using FPGAs and apply it to some data sets. the security evaluation and experimental results show that with this method, DNA sequence privacy is well protected, and the extra cost is acceptable.

关键词： field programmable gate arrays Encryption Kernel Privacy Cloud computing

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