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A placement algorithm for FPGA designs with multiple I/O standards 10th

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10th international conference on field-programmable logic and applications, fpl 2000

作者： Anderson, Jason Saunders, Jim Nag, Sudip Madabhushi, Chari Jayaraman, Rajeev Xilinx Inc. 2100 Logic Drive San JoseCA95124 United States

ISBN: (纸本)3540678999

State-of-the-art FPGAs possess I/O resources that can be configured to support a wide variety of I/O standards [1]. In such devices, the I/O resources are grouped into banks. One of the consequences of the banked organization is that all of the I/O objects that are placed within a bank must use „compatible"I/O standards. the compatibility of I/O standards is based on each standard’s supply and reference voltage requirements. For designs that use more than one I/O standard, the constraints associated with the banked organization lead to a constrained I/O pad placement problem. Meeting these constraints with a minimal deleterious effect on traditional objectives like minimizing wirelength turns out to be quite challenging. In this paper, we present a placement algorithm that operates in the context of these constraints. Our approach uses a combination of simulated annealing, weighted bipartite matching and constructive packing to produce a feasible I/O placement. Results show that the proposed algorithm produces placements with wirelength characteristics that are similar to the placements produced when pad placement is unconstrained. © Springer-Verlag Berlin Heidelberg 2000.

关键词： Simulated annealing

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Development of fully FPGA-based 3D (X, Y, t) detection systems using multi-channel Tapped-Delay-Line Time-to-Digital Converter with Cross Delay-Line detectors

Development of fully FPGA-based 3D (X, Y, t) detection syste...

引用

IEEE Nuclear Science Symposium and Medical Imaging conference (NSS/MIC) / 24th international Symposium on Room-Temperature Semiconductor X-Ray and Gamma-Ray Detectors

作者： Lusardi, N. Garzetti, F. Geraci, A. Cautero, G. Dri, C. Pittana, P. Sergo, R. Stebel, L. Politecn Milan DEIB Via Golgi 40 I-20133 Milan MI Italy Elettra Sincrotrone Trieste SS 14Km 1635 AREA Sci Pk I-34149 Trieste Italy

ISBN: (纸本)9781538622827

Time-resolved experiments often need detection devices able to provide information about position and arrival time of each detected event. Time resolution is a fundamental requirement for these devices, along with the high versatility and fast real-time computing of the acquisition system. Typical architectures, based on Time-to-Digital Converters (TDC) followed by a FPGA, combine very fast parallel computing with a time precision better than hundreds of picoseconds, allowing to perform state-of-the-art time-resolved experiments. Nevertheless, time resolution is still a limiting factor, in particular for imaging applications where the detector spatial resolution is determined through time measurement. Furthermore, the separation between the TDC devices and a readout FPGA has some drawbacks in terms of versatility of the system. In this article, we present a new approach, combining FPGA-based multi-channel Tapped-Delay-Line TDC and an efficient multipurpose readout logic, to greatly improve the overall performance and versatility of Cross Delay-Line (CDL) detector systems.

关键词： Detectors field programmable gate arrays Time measurement Channel estimation Spatial resolution Synchrotrons Probes

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Design and implementation of an FPGA-based fuzzy MPPT controller for PV standalone systems

Design and implementation of an FPGA-based fuzzy MPPT contro...

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international conference on Microelectronics, ICM

作者： A. Messai A. Mellit A. Guessoum Laboratoire LATSI Universite Saad Dahlab de Blida Blida Algeria

In this paper, the design of an FPGA based digital fuzzy MPPT controller with the typical DC-DC boost converter is described. We have optimally designed the DC-DC converter intended for PV applications, developed the MPPT digital control function and implemented it on an FPGA circuit. Simulation results show that, the developed system was able to seek the instantaneous maximum power being produced by the PV in all environmental conditions.

关键词： Maximum power point trackers field programmable gate arrays DC-DC power converters Niobium Fuzzy logic Photovoltaic systems Hardware

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BitBlender: Scalable Bloom Filter Acceleration on FPGAs with Dynamic Scheduling

BitBlender: Scalable Bloom Filter Acceleration on FPGAs with...

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international conference on field programmable logic and applications

作者： Kenneth Liu Alec Lu Zhenman Fang HiAccel Lab Simon Fraser University Burnaby B.C Canada

ISBN: (数字)9798331530075

ISBN: (纸本)9798331530082

the Bloom filter is one of the most widely used data structures in big data analytics to efficiently filter out vast amounts of noisy data. Unfortunately, prior Bloom filter designs only focus on single-input-stream acceleration, and can no longer match the increasing data rates offered by modern *** support large Bloom filters with low false-positive rate and high throughput, we present BitBlender, a configurable and scalable multi-input-stream Bloom filter acceleration framework in HLS. To effectively share one large bit-vector on chip among all streams, we design and implement the novel arbiter and unshuffle modules to dynamically schedule conflicting accesses to execute sequentially and non-conflicting accesses to execute in parallel. To support different user configurations of the Bloom filter, we also develop an automation flow, together with an accurate performance estimator, to automatically generate the best BitBlender design. Experimental results show that, on the AMD/Xilinx Alveo U280 FPGA, BitBlender achieves a throughput up to 2,194 MQueries/s (i.e., $8.8 \mathrm{~GB} / \mathrm{s}$) for a $\mathrm{9 6 M b}$ bit-vector with 0.01% false-positive rate. It achieves up to 10.4x speedup over a 24-thread CPU implementation and up to 4.9x speedup over a naively-duplicated multi-stream FPGA design. BitBlender will be released soon at https://***/SFU-HiAccel/BitBlender.

关键词： Matched filters Schedules Automation Prevention and mitigation System recovery throughput System-on-chip logic field programmable gate arrays Streams

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Modular Signal Processing Unit for Motion Control applications Based on System-on-Chip with FPGA

Modular Signal Processing Unit for Motion Control Applicatio...

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international conference on Emerging Technologies and Factory Automation (ETFA)

作者： Vlastimil Šetka Ondřej Ježek Rihards Novickis NTIS – New Technologies for the Information Society Research Center University of West Bohemia Pilsen Czech Republic EDI – Institute of Electronics and Computer Science Riga Latvia

Motion control systems with distributed architecture where multiple input/output devices are connected to the upper layer controller by fast digital communication (fieldbus) became an industrial standard. this paper presents design of a modular input/output device which can process signals from multiple sensors, drive multiple actuators and act as a Slave or Master node in EtherCAT fieldbus network. User-defined algorithms can be easily implemented to preprocess input signals, combine multiple signals or close local control loops with extremely high sampling rates which makes the difference to standard off-the-shelf solutions. To meet these requirements and simplify hardware design, our device is based on System-on-Chip with both programmable logic (FPGA) and classic processor (CPU) ARM cores. Data processing including user algorithms can be done entirely in FPGA which provides very low latency and no jitter, and also on CPU for more complex computations with advantage of tight integration between FPGA and CPU. In this paper we provide description of hardware design, system architecture and typical applications.

关键词： field programmable gate arrays Universal Serial Bus Central Processing Unit Hardware Ethernet Random access memory

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A Flexible Profiling Sub-System for Reconfigurable logic Architectures

A Flexible Profiling Sub-System for Reconfigurable Logic Arc...

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Euromicro conference on Parallel, Distributed and Network-Based Processing

作者： G. Valente V. Muttillo L. Pomante F. Federici M. Faccio A. Moro S. Ferri C. Tieri DEWS Center of Excellence Università Degli Studi Dell'Aquila L'Aquila Italy

In recent years, embedded applications have been characterized by increasingly stringent requirements, both from functional and non-functional point of view. this led to the adoption of complex hardware platforms (multi-core and many-core architectures), able to guarantee high computational power with low energy consumption and reduced footprint. An efficient characterization of these platforms can be problematic, given the large number of hardware resources and the complexity of software applications. For this reason, the need for a runtime analysis support should be taken in account during the design phase (a design "for monitorability"). this paper introduces "Adaptive Profiling Hardware Sub-system" (AIPHS), a hardware profiling tool supporting the development of runtime monitorable systems. Two different multicore platforms are considered in order to evaluate AIPHS functionalities: an asymmetric dual-MicroBlaze system and a quad-Leon3 system supporting symmetric multiprocessing.

关键词： FPGAs Leon3 MicroBlaze Multi-core architectures OpenMP Profiling core construction symmetric multiprocessor Reconfigurable logic field programmable gate arrays ARCHITECTURE hardware resource applications software low energy consumption computational power Platform design phases Runtime

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Hardware Accelerator for Edge Detection

Hardware Accelerator for Edge Detection

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IEEE international conference on Intelligent Engineering Systems (INES)

作者： Aous H. Kurdi Janos L. Grantner Ikhlas Abdel-Qader Department of Electrical and Computer Engineering Western Michigan University Kalamazoo MI USA

ISBN: (数字)9781728110592

ISBN: (纸本)9781728110608

Hardware accelerators have been recently proposed for computationally extensive applications like real-time video image processing systems. Contemporary hardware accelerators are implemented by using either field programmable Gate Array (FPGA) or System-on-Chip (SoC) devices. Edge detection is a fundamental task for any image processing system. In this paper, a pipelined architecture for a fuzzy logic edge detection system is proposed. the system has been implemented and tested on various Xilinx 7 Series devices. the hardware accelerator core utilizes a pipeline of seven stages. Depending on the available resources the accelerator system can be made up of several cores operating simultaneously. A single-core implementation of the system can process a 1080P HD test frame at a rate of about 45 frames per second. It outperforms its software counterpart by a factor of ten thousand.

关键词： Hardware Image edge detection Fuzzy logic Pipelines field programmable gate arrays Real-time systems

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Reconfigurable Computing Middleware for Application Portability and Productivity

Reconfigurable Computing Middleware for Application Portabil...

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IEEE international conference on Application-specific Systems, Architectures and Processors

作者： Robert Kirchgessner Alan D. George Herman Lam NSF Center for High-Performance Reconfigurable Computing (CHREC) Department of Electrical and Computer Engineering University of Florida Gainesville Florida 32611-6200

ISBN: (纸本)9781479904945

Reconfigurable computing (RC) devices such as field-programmable gate arrays (FPGAs) offer significant advantages over fixed-logic, many-core CPU and GPU architectures, including increased performance for many computationally challenging applications, superior power efficiency, and recon-figurability. Difficulties of using FPGAs, however, has limited their acceptance in high-performance computing (HPC) and high-performance embedded computing (HPEC) applications. these difficulties stem from a lack of standards between FPGA platforms and the complexities of hardware design, and lead to higher costs and time to market over competing technologies. Differences in FPGA platform resources such as the type and number of FPGAs, memories and interconnects, as well as vendor-specific procedural APIs and hardware interfaces, inhibits application portability and code reusability. Despite efforts to reduce FPGA application design complexity through technologies such as high-level synthesis (HLS) tools, platform support and portability remains limited, and is typically left as a challenge for application developers. In this paper, we present a novel RC Middleware (RCMW), an extensible framework which enables FPGA application portability and enhances developer productivity by providing an application-centric development environment. Developers focus specifically on the optimal resources and interfaces required by their application, and RCMW handles the mapping and translation of those resources onto a target platform. We demonstrate that RCMW enables application portability over three heterogeneous platforms from two vendors, using both Xilinx and Altera FPGAs, with less than 10% performance and area overhead for several application kernels, and microbench-marks for the common case. We present the productivity benefits of RCMW, showing that RCMW reduces required number of hardware and software driver lines of code and total development time with respect to native platform deployme

关键词： FPGA portability productivity reconfigurable computing Portability field programmable gate arrays productivity development time Platform

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A High-speed Scanning Module Based on a DBR Tunable Laser for FBG Sensor Systems

A High-speed Scanning Module Based on a DBR Tunable Laser fo...

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international conference on Transparent Optical Networks

作者： Wenqian Yuan Kun Shang Chongqian Zhu Haikun Zhang Yanan Zhai Xingwei Sun Yaping Zhang University of Jinan Jinan Shandong China Shandong Institute of Industrial Technology Innovation Park Jinan Shandong China OptoChip Optoelectronics Ltd B120 Qilu Soft Park Jinan China

ISBN: (数字)9798350377323

ISBN: (纸本)9798350377330

As some physical parameter measurements (e.g. vibration) require a high-speed FBG demodulation system, a high-speed scanning module as the core part of this system is investigated. In this study, the design and implementation of a high-speed scanning module for Fiber Bragg Grating (FBG) sensing based on a Distributed Bragg Reflector (DBR) tunable laser and a field programmable Gate Array (FPGA) is presented. the innovatively designed and constructed high-speed FBG sensor system comprises a DBR laser, a laser drive circuit with self-programmed control algorithms, and a signal processing module. the overall performance of this high-speed FBG sensor system is evaluated and verified experimentally in terms of the validation of scanning rate, accuracy and stability. this high-speed FBG sensor system has opened a wide range of unique applications for the measurement of a variety of key physical parameters which require a high-speed FBG demodulation technique.

关键词： Vibrations Laser theory Measurement by laser beam logic gates Fiber gratings Sensor systems Distributed Bragg reflectors

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PC-BNA: Parallel Convolution Binary Neural Network Accelerator

PC-BNA: Parallel Convolution Binary Neural Network Accelerat...

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IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Haihui Liu Yuang Zhang Xiangwei Zheng Mengxin Yu Baoxu An Xiaojie Liu Shandong Provincial Key Laboratory for Distributed Computer Software Novel Technology School of Information Science and Engineering Shandong Normal University Jinan China

Binary neural network (BNN) is widely used in speech recognition, image processing and other fields to save memory and speed up computing. However, the accuracy of the existing binarization scheme in the realistic dataset is obviously low, and the input layer uses 32-bit floating point to avoid excessive precision loss, which requires additional computing units and increases the computational burden. therefore, it is very important to improve the input layer, save computing resources and reduce precision loss. In this paper, we propose a parallel convolution binary neural network accelerator architecture (PC-BNA). Based on our proposed BNN model, we design an efficient field programmable gate array (FPGA) based accelerator. the input of the first layer is binarized, the traditional binary convolution layer is replaced by a parallel binary convolution, and the network building blocks are improved. the experimental results show that the proposed PC-BNA has higher accuracy and better performance on CIFAR-10. the image recognition accuracy is as high as 91.4%, which is superior to the state-of-art of the BNN accelerator. Compared to the state-of-the-art BNN model, when using the same model size, the use of look-up-table (LUT) saves 9.08%, and the digital signal processor (DSP) saves 27.7%. the results suggest that it is promising for PC-BNA in future high performance mobile artificial intelligence applications.

关键词： Performance evaluation Convolution Neural networks Digital signal processors Speech recognition logic gates Mobile handsets

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