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Hierarchical reconfiguration of FPGAs 24

Hierarchical reconfiguration of FPGAs

引用

24th international conference on field programmable logic and applications, fpl 2014

作者： Koch, Dirk Beckhoff, Christian University of Manchester United Kingdom University of Oslo Norway

ISBN: (纸本)9783000446450

Partial reconfiguration allows some applications to substantially save FPGA area by time sharing resources among multiple modules. In this paper, we push this approach further by introducing hierarchical reconfiguration where reconfigurable modules can have reconfigurable submodules. this is useful for complex systems where many modules have common parts or where modules can share components. For such systems, we show that the number of bitstreams and the bitstream storage requirements can be scaled down from a multiplicative to an additive behavior with respect to the number of modules and submodules. A case study consisting of different reconfigurable softcore CPUs and hierarchically reconfigurable custom instruction set extensions demonstrates a 18.7× lower bitstream storage requirement and up to 10× faster reconfiguration speed when using hierarchical reconfiguration instead of using conventional single-level module-based reconfiguration. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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Fast and accurate SEU-tolerance characterization method for Zynq SoCs 24

Fast and accurate SEU-tolerance characterization method for ...

引用

24th international conference on field programmable logic and applications, fpl 2014

作者： Villata, Igor Bidarte, Unai Kretzschmar, Uli Astarloa, Armando Lazaro, Jesus Department of Electronics and Telecommunications University of the Basque Country UPV/EHU Bilbao Spain

ISBN: (纸本)9783000446450

In this paper a new SEU (Single Event Upset) emulation method for testing fault tolerant systems in FPGAs is presented. It is implemented on a 'Xilinx Zynq®-7000 All programmable System on Chip (SoC)' device, which combines a hard microprocessor with programmable logic. An important new feature is that an internal hardware configuration interface controlled by this microprocessor is provided. this interface is used for injecting faults into the configuration bitstream in order to emulate radiation effects. Since both the processing system and the programmable logic are in the same chip, this method has the high speed characteristics of internal fault injection methods. As a hard internal configuration interface is provided, a configuration bit belonging to the internal interface port cannot be flipped and injection side effects are avoided. this method is especially suitable for testing complex real fault-tolerant FPGA designs because no substantial modifications need to be added to the original design. A universal verification system is proposed to avoid designing complex external application-dependent testbenches. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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Pipelined compressor tree optimization using integer linear programming 24

Pipelined compressor tree optimization using integer linear ...

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24th international conference on field programmable logic and applications, fpl 2014

作者： Kumm, Martin Zipf, Peter University of Kassel Digital Technology Group Germany

ISBN: (纸本)9783000446450

Compressor trees offer an effective realization of the multiple input addition needed by many arithmetic operations. However, mapping the commonly used carry save adders (CSA) of classical compressor trees to FPGAs suffers from a poor resource utilization. this can be enhanced by using generalized performance counters (GPCs). Prior work has shown that high efficient GPCs can be constructed by exploiting the low-level structure of the FPGA. However, due to their irregular shape, the selection of those is not straight forward. Furthermore, the compressor tree has to be pipelined to achieve the potential FPGA performance. then, a selection between registered GPCs or flip-flops has to be done to balance the pipeline. this work defines the pipelined compressor tree synthesis as an optimization problem and proposes a (resource) optimal method using integer linear programming (ILP). Besides that, two new GPC mappings with high efficiency are proposed for Xilinx FPGAs. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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Achieving portability and efficiency over chip heterogeneous multiprocessor systems 24

Achieving portability and efficiency over chip heterogeneous...

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24th international conference on field programmable logic and applications, fpl 2014

作者： Cartwright, E. Sadeghian, Alborz Ma, Sen Andrews, David Dept. of Computer Science and Computer Engineering University of Arkansas Fayetteville United States

ISBN: (纸本)9783000446450

Emerging programming models for chip heterogeneous multiprocessor (CHMP) systems elevate architecture details up into the source code. this eliminates portability and requires designers to navigate a multidimensional search space when trying to optimize designs. In this paper, we present an approach that reinstates portability through a combination of polymorphic functions and an adaptive runtime system. Together they enable runtime profiling and dynamic scheduling of unaltered source code across systems with different combinations of heterogeneous resources. Our results verify the ability of our programming model and runtime system to re-enable the notion of writing code once and run anywhere. Runtime results show how runtime tuning can increase resource utilization and provide performance increases as the number and heterogeneity of computing resources increases. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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Efficient multi-standard cognitive radios on FPGAs 24

Efficient multi-standard cognitive radios on FPGAs

引用

24th international conference on field programmable logic and applications, fpl 2014

作者： Pham, thinh H. Fahmy, Suhaib A. McLoughlin, Ian Vince School of Computer Engineering Nanyang Technological University Singapore Singapore School of Information Science and Technology University of Science and Technology of China Hefei China

ISBN: (纸本)9783000446450

Cognitive radios that support multiple standards and modify operation depending on environmental conditions are becoming more important as the demand for higher bandwidth and efficient spectrum use increases. Traditional implementations in custom ASICs cannot support such flexibility, with standards changing at a faster pace, while software baseband implementations fail to achieve the performance required. Hence, FPGAs offer an ideal platform bringing together flexibility, performance, and efficiency. this work explores the possible techniques for designing multi-standard radios on FPGAs, and explores how partial reconfiguration can be leveraged in a way that is amenable for domain experts with minimal FPGA knowledge. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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Experimental multi-FPGA GNSS receiver platform 24

Experimental multi-FPGA GNSS receiver platform

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24th international conference on field programmable logic and applications, fpl 2014

作者： Garzia, Fabio Rugamer, Alexander Koch, Robert Neumaier, Philipp Serezhkina, Ekaterina Overbeck, Matthias Rohmer, Gunther Fraunhofer IIS Nuremberg Germany

ISBN: (纸本)9783000446450

this paper describes the system architecture and implementation results of a robust and flexible dual-frequency 2×2 array processing GNSS receiver platform. A digital front-end FPGA pre-processes the incoming raw ADC data and implements interference mitigation methods in time and frequency domain. An optional second FPGA card can be used to realize more sophisticated and computational complex interference mitigation techniques. Finally, the data stream is processed on a baseband FPGA platform with spatial array processing techniques using a software assisted hardware GNSS receiver approach. the interconnection of the FPGAs is realized using gigabit transceivers handling a constant raw data rate of 16.8 Gbit/s. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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DyRACT: A partial reconfiguration enabled accelerator and test platform 24

DyRACT: A partial reconfiguration enabled accelerator and te...

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24th international conference on field programmable logic and applications, fpl 2014

作者： Vipin, Kizheppatt Fahmy, Suhaib A. School of Computer Engineering Nanyang Technological University Singapore Singapore

ISBN: (纸本)9783000446450

Integrating FPGAs with a general purpose computer remains difficult, but recent efforts have resulted in open frameworks that offer a software API and hardware interface to allow easier integration. However, such systems only support static FPGA designs. With the addition of partial reconfiguration (PR) support, such frameworks can enable more effective use of FPGAs. Now, designers can incorporate hardware accelerators within their software applications, and these can be loaded dynamically as required. We present a PR-enabled FPGA platform that allows user modules to be loaded onto the FPGA, inputs to be applied, results obtained, and functions to be swapped at runtime. the interface and PR management logic are part of the static region, while multiple accelerators can be loaded using high level functions provided by the API. Reconfiguration and data transfer are both managed over the PCIe interface from the host PC, with communication throughput of more than 1.5 GB/s (75% of peak PCIe bandwidth) and reconfiguration of a large accelerator in 20 ms. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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Improving FPGA accelerated tracking with multiple online trained classifiers 24

Improving FPGA accelerated tracking with multiple online tra...

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24th international conference on field programmable logic and applications, fpl 2014

作者： Jacobsen, Matthew Sampangi, Siddarth Freund, Yoav Kastner, Ryan Computer Science and Engineering University of California San Diego United States

ISBN: (纸本)9783000446450

Robust real time tracking is a requirement for many emerging applications. Many of these applications must track objects even as their appearance changes. Training classifiers online has become an effective approach for dealing with variability in object appearance. Classifiers can learn and adapt to changes online at the cost of additional runtime computation. In this paper, we propose a FPGA accelerated design of an online boosting algorithm that uses multiple classifiers to track and recover objects in real time. Our algorithm uses a novel method for training and comparing pose-specific classifiers along with adaptive tracking classifiers. Our FPGA accelerated design is able to track at 60 frames per second while concurrently evaluating 11 classifiers. this represents a 30× speed up over a CPU based software implementation. It also demonstrates tracking accuracy at state of the art levels on a standard set of videos. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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A bit-interleaved embedded hamming scheme to correct single-bit and multi-bit upsets for SRAM-based FPGAs 24

A bit-interleaved embedded hamming scheme to correct single-...

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24th international conference on field programmable logic and applications, fpl 2014

作者： Venkataraman, Shyamsundar Santos, Rui Das, Anup Kumar, Akash Department of Electrical and Computer Engineering National University of Singapore Singapore Singapore

ISBN: (纸本)9783000446450

Single Event Upsets (SEUs) inadvertently change the configuration bits of Static-RAM (SRAM)-based field programmable Gate Arrays (FPGAs), leading to erroneous output until the error has been corrected. Scrubbing using an Error Correction Code (ECC) such as hamming is a popular method to correct such faults. However, current works either require a large external memory to store the ECCs or can at most correct only one error in a frame. this paper proposes a novel bit-interleaved embedded hamming scheme along with scrubbing, to correct single (SBUs) and multi-bit upsets (MBUs) in SRAM-based FPGAs. this scheme does not require an external memory to store the ECCs, as they are embedded within the configuration memory itself. Experiments conducted on various benchmarks show that the proposed scheme can handle multiple errors per frame very well, with an embedding efficiency of over 99.3%. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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Using high-level knowledge to enhance data channels in FPGA streaming systems 24

Using high-level knowledge to enhance data channels in FPGA ...

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24th international conference on field programmable logic and applications, fpl 2014

作者： Wijeyasinghe, Marlon thomas, David Department of Electrical and Electronic Engineering Imperial College London United Kingdom

ISBN: (纸本)9783000446450

FPGAs are commonly used in high performance computing applications, often in the form of streaming systems which exploit parallelism of algorithms along pipelined kernels. While such applications have traditionally been designed at the Register Transfer Level (RTL), the increasing complexity in terms of FPGA resource usage, arithmetic logic and dataflow is causing the time taken for RTL programming to be prohibitive. this necessitates using high-level programming tools to transpar-ently handle low-level aspects - thus simplifying the design pro-cess. Examples of high-level tools for building streaming systems include MaxCompiler by Maxeler Technologies and DSP Builder by Altera. We propose an interception layer which when inserted into communication channels, transparently enhances their per-formance and capabilities without needing to modify the stream-ing kernels or host code. We discuss specific channel enhance-ments: lossless compression to improve effective bandwidth;error correction and fault tolerance to improve reliability. the interception layer is intended to add complex behaviour while maintaining the simplicity of the high-level abstraction when transmitting data via a channel. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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