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检索条件"任意字段=25th International Conference on Field Programmable Logic and Applications, FPL 2015"

共 149 条记录，以下是1-10 订阅

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25th international conference on field programmable logic and applications, fpl 2015

25th International Conference on Field Programmable Logic an...

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25th international conference on field programmable logic and applications, fpl 2015

ISBN: (纸本)9780993428005

the proceedings contain 97 papers. the topics discussed include: using island-style bi-directional intra-CLB routing in low power FPGAs;energy efficient partitioning of dynamic reconfigurable MRAM-FPGAs;automatic support for multi-module parallelism from computational patterns;fine-tuning CLB placement to speed up reconfigurations in NVM-based FPGAs;a technology mapper for depth-constrained FPGA logic cells;parallel feature extraction and heterogeneous object-detection for multi-camera driver assistance systems;generating FPGA accelerators for chemical similarity assessment;7MOPS/lemon-battery image processing demonstration with an ultra-low power reconfigurable accelerator CMA-SOTB-2;NetFPGA - rapid prototyping of high bandwidth devices in open source;optimizing energy efficient low-swing interconnect for sub-threshold FPGAs;reduction calculater in an FPGA based switching hub for high performance clusters;and serial and parallel interleaved modular multipliers on FPGA platform.

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DESIGN AND SIMULATION TOOLS FOR EMBEDDED NOCS ON FPGAS 25

DESIGN AND SIMULATION TOOLS FOR EMBEDDED NOCS ON FPGAS

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25th international conference on field programmable logic and applications

作者： Abdelfattah, Mohamed S. Bitar, Andrew Yaghi, Ange Betz, Vaughn Univ Toronto Dept Elect & Comp Engn Toronto ON Canada

We propose embedding hard NoCs on FPGAs to improve system-level communication as detailed in our previous studies [1-6]. this demo paper outlines the three main design and simulation tools that we have been using to e... 详细信息

ISBN: (纸本)9781467381239

关键词： simulation tool field programmable gate arrays embedding

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High-Level FPGA logic Synthesis from. NET Programs for Software Developers the Hastlayer Project 25

High-Level FPGA Logic Synthesis from. NET Programs for Softw...

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25th international conference on field programmable logic and applications

作者： Lehoczky, Zoltan Toth, Richard Somogyi, Krisztian Lombiq Technol Ltd Budapest Hungary

ISBN: (纸本)9781467381239

FPGA circuit design, and thus the unique computing power of FPGAs is currently mostly only accessible to experts working in the field. the Hastlayer project aims to give a tool to software developers familiar with the. NET platform to automatically transform performance-critical parts of their programs into seamlessly usable FPGA-implemented hardware, yielding faster program execution and lower power consumption.

关键词： FPGA High-Level Synthesis .NET

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FPGA-based All-digital Transmitters 25

FPGA-based All-digital Transmitters

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25th international conference on field programmable logic and applications

作者： Cordeiro, R. F. Oliveira, Arnaldo S. R. Vieira, Jose Univ Aveiro DETI Inst Telecomunicaes Aveiro Portugal

ISBN: (纸本)9781467381239

this paper presents the architecture and implementation of an FPGA-based all digital transmitter for wireless radio communications. these transmitters allow a greater degree of flexibility for the carrier frequency, signal bandwidth and the use of simultaneous multiple-standards. Latest advances in the state-of-the-art in this emerging area are presented as well as the remaining issues to he solved and the proposed architecture to address some them.

关键词： Flexibility Transmitters field programmable gate arrays Building construction ARCHITECTURE Radiocommunication signal bandwidth

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Placing Partially Reconfigurable Stream Processing applications on FPGAs 25

Placing Partially Reconfigurable Stream Processing Applicati...

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25th international conference on field programmable logic and applications

作者： Grigore, Nicolae Bogdan Koch, Dirk Univ Manchester Manchester M13 9PL Lancs England

ISBN: (纸本)9781467381239

Finding placement locations for modules on an FPGA in a limited amount of time is a crucial task that determines the efficiency of a dynamic partially reconfigurable system. In this work, we will define a placement method based on transforming the inherent two dimensional (2D) structure of the FPGA into a one dimensional string and employing string matching. Moreover, our model is suited to compute a module placement over multiple chained reconfigurable regions. Our algorithm is based on a hybrid approach consisting of an offline precompute phase at design-time which in turn is used to speed-up module placement at run-time.

关键词： field programmable gate arrays configurability placement Runtime design year

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Significant Papers from the First 25 Years of the fpl conference 25

Significant Papers from the First 25 Years of the FPL Confer...

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25th international conference on field programmable logic and applications

作者： Leong, Philip H. W. Amano, Hideharu Anderson, Jason Bertels, Koen Cardoso, Joao M. P. Diessel, Oliver Gogniat, Guy Hutton, Mike Lee, JunKyu Luk, Wayne Lysaght, Patrick Platzner, Marco Prasanna, Viktor K. Rissa, Tero Silvano, Cristina So, Hayden Wang, Yu Univ Sydney Sydney NSW 2006 Australia Keio Univ Tokyo 108 Japan Univ Toronto Toronto ON M5S 1A1 Canada Delft Univ Technol NL-2600 AA Delft Netherlands Univ Porto P-4100 Oporto Portugal Univ NSW Kensington NSW Australia Univ South Brittany Lorient France Altera Corp San Jose CA USA Imperial Coll London London England Xilinx Res Labs San Jose CA USA Univ Paderborn Paderborn Germany Univ Southern Calif Los Angeles CA USA Nokia Espoo Finland Politecn Milan Milan Italy Univ Hong Kong Hong Kong Hong Kong Peoples R China Tsinghua Univ Beijing Peoples R China

the list of significant papers from the first 25 years of the field-programmable logic and applications conference (fpl) is presented in this paper. these 27 papers represent those which have most strongly influenced ...

ISBN: (纸本)9781467381239

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Mind the (Synthesis) Gap: Examining Where Academic FPGA Tools Lag Behind Industry 25

Mind The (Synthesis) Gap: Examining Where Academic FPGA Tool...

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25th international conference on field programmable logic and applications

作者： Hung, Eddie Imperial Coll London Dept Comp London England

ISBN: (纸本)9781467381239

Firstly, we present VTR-to-Bitstream v2.0, the latest version of our open-source toolchain that takes Verilog input and produces a packed, placed-and now routed - solution that can be programmed onto the Xilinx commercial FPGA architecture. Secondly, we apply this updated tool to measure the gap between academic and industrial FPGA tools by examining the quality of results at each of the three main compilation stages: synthesis, packing & placement, routing. Our findings indicate that the delay gap (according to Xilinx static timing analysis) for academic tools breaks down into a 31% degradation with synthesis, 10% with packing & placement, and 15% with routing. this leads us to believe that opportunities for improvement exist not only within VPR, but also in the front-end tools that lie upstream.

关键词： field programmable gate arrays (FPGA)

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FPGA-based All-digital Software Defined Radio System Demonstration 25

FPGA-based All-digital Software Defined Radio System Demonst...

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25th international conference on field programmable logic and applications

作者： Cordeiro, Rui F. Prata, Andre Oliveira, Arnaldo S. R. Carvalho, Nuno Borges Vieira, Jose N. Univ Aveiro DETI Inst Telecomunicacoes Aveiro Portugal

ISBN: (纸本)9781467381239

All-digital radios allow the full digitalization of the radio system which poses an important step towards the complete software description of RF signals proposed in SDR. Using digital signal processing techniques and the integration of the radio into a single digital chip, it is expected that high flexibility in these systems will be fundamental for the next generation of wireless networks. In addition, FPGA-based architectures take advantage of the high and heterogeneous processing power of modern FPGAs as well as their dynamic configurability capabilities needed for highly flexible radio transceivers.

关键词： field programmable gate arrays (FPGA)

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Variable-Latency Signed Addition on FPGAs 25

Variable-Latency Signed Addition on FPGAs

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25th international conference on field programmable logic and applications

作者： Cilardo, Alessandro Univ Naples Federico II Dept Elect Engn & Informat Technol Via Claudio 21 I-80125 Naples Italy

ISBN: (纸本)9781467381239

Variable-latency, or speculative, addition is an effective technique to implement fast adders working on very long operands. Most approaches to speculative addition are either based on the assumption that operands have equiprobable independent bits, which is rarely the case in real applications due to sign-extension, or they can handle the case of signed numbers at the price of a considerable area overhead. Furthermore, many existing approaches require ad-hoc schemes preventing the reuse of standard adders typically available as optimized library components in many technologies, most notably field-programmable Gate Arrays. this paper introduces an innovative scheme for speculative addition that effectively addresses both problems, yielding fast and low-area circuits able to handle sign-extended numbers speculatively and only made of optimized carry-propagation adders based on fast carry circuitry as basic building blocks.

关键词： field programmable gate arrays adders Fasting Electric circuits Signed Addition reaction reuse programmable gate array Handles operand basic component

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In-field Vulnerability Analysis of Hardware-Accelerated Computer Vision applications 25

In-Field Vulnerability Analysis of Hardware-Accelerated Comp...

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25th international conference on field programmable logic and applications

作者： Chadjiminas, I. Kyrkou, C. theocharides, T. Michael, M. K. Ttofis, C. Univ Cyprus KIOS Res Ctr Intelligent Syst & Networks Dept Elect & Comp Engn Nicosia Cyprus ACC Innovat Ltd Nicosia Cyprus

ISBN: (纸本)9781467381239

In this paper, we propose an FPGA-based emulation framework that can provide dynamic vulnerability analysis for hardware-accelerated computer vision applications. the framework can be integrated alongside the targeted application, to allow for run-time, in-field, dynamically adjusted vulnerability analysis in real-world conditions, taking into consideration the non-deterministic parameters of the computer vision algorithm computations. We evaluate the proposed framework in real-time using an FPGA platform, for an obstacle avoidance (OA) computer vision application and its disparity estimation kernel to study the impact of Single-Event Upsets (SEUs).

关键词： Approximate Computing FPGA Single Event Upsets Intermittent Faults Transient Faults Computer Vision Reliability and Vulnerability Analysis

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