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检索条件"任意字段=25th International Conference on Field Programmable Logic and Applications, FPL 2015"

共 149 条记录，以下是71-80 订阅

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Energy optimization of FPGA-based stream-oriented computing with power gating

Energy optimization of FPGA-based stream-oriented computing ...

引用

international conference on field programmable logic and applications

作者： Mohammad Hosseinabady Jose Luis Nunez-Yanez Department of Electrical and Electronic Engineering University of Bristol UK

In this paper, we propose a technique to improve the energy efficiency of FPGA devices by exploiting power gating during idle periods in streaming applications. the main idea is to shuffle idle periods during application execution so that the energy and timing overheads of turning the FPGA on and off can become acceptable. A key requirement is that fast FPGA-based accelerators are available and that the application follows a repetitive nature of execution. In this case, the accelerators work on a successive computing mode to accumulate the idle intervals in different iterations in order to make power gating feasible. Streaming on demand applications which are ubiquitous in embedded and portable devices are very good candidates to benefit from this technique. A case study is presented based on an MP3 player as the streaming application which shows up to 52.9% energy reduction.

关键词： field programmable gate arrays Energy consumption Schedules Power demand Computational modeling Delays

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UniStream: A unified stream architecture combining configuration and data processing

UniStream: A unified stream architecture combining configura...

引用

international conference on field programmable logic and applications

作者： Jian Yan Jifang Jin Ying Wang Xuegong Zhou Philip Leong Lingli Wang State Key Laboratory of ASIC and System Fudan University Shanghai China School of Electrical and Information Engineering The University of Sydney Australia

this paper proposes UniStream, a unified stream architecture based on point-to-point stream channels combining both bitstream configuration and data stream processing. In addition, unified APIs are provided to support bitstream configuration and data stream processing, as well as the stream interconnect. A cost model is also presented for the overhead on the stream interconnect, hardware task configuration and data stream processing at system level, which can be used during the early stage of development. the flexibility and high efficiency of UniStream are demonstrated on Xilinx Virtex-5 and Virtex-6 FPGAs. Experimental results on bitstream configuration/ read-back, data encryption/decryption and Discrete Cosine Transformation show that performance can be significantly improved with different stream modes.

关键词： Hardware Computer architecture field programmable gate arrays System-on-chip throughput Software Data models

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Optimised OpenCL workgroup synthesis for hybrid ARM-FPGA devices

Optimised OpenCL workgroup synthesis for hybrid ARM-FPGA dev...

引用

international conference on field programmable logic and applications

作者： Mohammad Hosseinabady Jose Luis Nunez-Yanez Department of Electrical and Electronic Engineering University of Bristol UK

this paper presents a workgroup synthesis mechanism to compile an OpenCL kernel to FPGA-based accelerators embedded in a multi-core CPU system-on-a-chip (SoC). the OpenCL kernels considered in this paper exhibit regular data access patterns. Coping with the limited amount of internal memory in embedded FPGAs, the workgroup synthesis utilises a novel data access pattern formulation to describe the parallelism already provided by the OpenCL kernels. To provide an OpenCL framework prototype to validate the proposed technique, a source-to-source compiler that transforms the OpenCL kernel into C/C++ code is developed. then vendor-specific high-level synthesis tools are used to convert the C/C++ code into the FPGA bitstream. Results based on popular real applications show up to 89.8% improvement in the execution time compared to other commercial FPGA OpenCL implementations.

关键词： field programmable gate arrays Kernel Parallel processing Hardware Arrays Optimization System-on-chip

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FPGA based nonlinear Support Vector Machine training using an ensemble learning

FPGA based nonlinear Support Vector Machine training using a...

引用

international conference on field programmable logic and applications

作者： Mudhar Bin Rabieah Christos-Savvas Bouganis Department of Electrical and Electronic Engineering Imperial College London

Support Vector Machines (SVMs) are powerful supervised learning methods in machine learning. However, their applicability to large problems has been limited due to the time consuming training stage whose computational cost scales quadratically with the number of examples. In this work, a complete FPGA-based system for nonlinear SVM training using ensemble learning is presented. the proposed framework builds on the FPGA architecture and utilizes a cascaded multi-precision training flow, exploits the heterogeneity within the training problem by tuning the number representation used, and supports ensemble training tuned to each internal memory structure so to address very large datasets. Its performance evaluation shows that the proposed system achieves more than an order of magnitude better results compared to state-of-the-art CPU and GPU-based implementations.

关键词： Training Support vector machines field programmable gate arrays Kernel Hardware Computer architecture Acceleration

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A scalable FPGA architecture for nonnegative least squares problems

A scalable FPGA architecture for nonnegative least squares p...

引用

international conference on field programmable logic and applications

作者： Alric Althoff Ryan Kastner Computer Science and Engineering University of California San Diego

Nonnegative least squares (NNLS) optimization is an important algorithmic component of many problems in science and engineering, including image segmentation, spectral deconvolution, and reconstruction of compressively sensed data. Each of these areas can benefit from high performance implementations suitable for embedded applications. Unfortunately, the NNLS problem has no solution expressible in closed-form, and many popular algorithms are not amenable to compact and scalable hardware implementation. Classical iterative algorithms generally have a per-iteration computational cost with cubic growth, and interdependencies which limit parallel approaches. In this paper we develop two efficient hardware architectures. One is based on a novel algorithm we develop in this paper specifically to reduce FPGA area consumption while preserving performance. We implement our architectures on a very small FPGA and apply them to reconstruction of a compressively sensed signal showing residual error results competitive with traditional algorithms.

关键词： Hardware field programmable gate arrays Convergence Algorithm design and analysis Random access memory Computer architecture Optimization

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Synthesizable FPGA fabrics targetable by the Verilog-to-Routing (VTR) CAD flow

Synthesizable FPGA fabrics targetable by the Verilog-to-Rout...

引用

international conference on field programmable logic and applications

作者： Jin Hee Kim Jason H. Anderson Dept. of Electrical and Computer Engineering University of Toronto Toronto ON Canada

We consider implementing FPGAs using a standard cell design methodology, and present a framework for the automated generation of synthesizable FPGA fabrics. the open-source Verilog-to-Routing (VTR) FPGA architecture evaluation framework [1] is extended to generate synthesizable Verilog for its in-memory FPGA architectural device model. the Verilog can be synthesized into standard cells, placed and routed using an ASIC design flow. A second extension to VTR generates a configuration bitstream for the FPGA; that is, the bitstream configures the FPGA to realize a user-provided placed and routed design. the proposed framework and methodology opens the door to silicon implementation of a wide range of VTR-modelled FPGA fabrics. In an experimental study, area and timing-optimized FPGA implementations in 65nm TSMC standard cells are compared with a 65nm Altera commercial FPGA.

关键词： field programmable gate arrays Microprocessors Routing Video recording Hardware design languages Table lookup

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Accurate power analysis for near-Vt RRAM-based FPGA

Accurate power analysis for near-Vt RRAM-based FPGA

引用

international conference on field programmable logic and applications

作者： Xifan Tang Pierre-Emmanuel Gaillardon Giovanni De Micheli École Polytechnique Fédérale de Lausanne (EPFL) Switzerland

Resistive Random Access Memory (RRAM)-based FPGA architectures employ RRAMs not only as memories to store the configuration but embed them in the datapaths of programmable routing resources to propagate signals with improved performances. Sources of power consumption have been intensively studied for conventional Static Random Access Memories (SRAM)-based FPGAs. However, very limited works focused so far on studying the power characteristics of RRAM-based FPGAs. In this paper, we first analyze the power characteristics of RRAM-based multiplexer at circuit level and then use electrical simulations to study power consumption of RRAM-based FPGA architectures. Experimental results show that RRAM-based FPGAs achieve a Power-Delay Product reduced by 50% compared to SRAM-based FPGA at nominal voltage and 20% compared to near-V t SRAM-based FPGA, respectively.

关键词： field programmable gate arrays Multiplexing Random access memory Power demand Routing Transistors Programming

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Efficient assembly for high order unstructured FEM meshes

Efficient assembly for high order unstructured FEM meshes

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international conference on field programmable logic and applications

作者： Pavel Burovskiy Paul Grigoras Spencer Sherwin Wayne Luk Department of Computing Imperial College London Department of Aeronautics Imperial College London

the Finite Element Method (FEM) is a common numerical technique used for solving Partial Differential Equations (PDEs) on complex domain geometries. Large and unstructured FEM meshes are used to represent the computation domains which makes an efficient mapping of the Finite Element Method onto FPGAs particularly challenging. the focus of this paper is on assembly mapping, a key kernel of FEM, which induces the sparse and unstructured nature of the problem. We translate FEM vector assembly mapping into data access scheduling to perform vector assembly directly on the FPGA, as part of the hardware pipeline. We show how to efficiently partition the problem into dense and sparse sub-problems which map well onto FPGAs. the proposed approach, implemented on a single FPGA could outperform highly optimised FEM software running on two Xeon E5-2640 processors.

关键词： Sparse matrices Finite element analysis Assembly field programmable gate arrays Kernel Hardware Arrays

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FPGA-based all-digital software defined radio system demonstration

FPGA-based all-digital software defined radio system demonst...

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international conference on field programmable logic and applications

作者： Rui F. Cordeiro André Prata Arnaldo S. R. Oliveira Nuno Borges Carvalho José N. Vieira Universidade de Aveiro DETI - Instituto de Telecomuniçõacoes Universidade de Aveiro Aveiro Aveiro PT

All-digital radios allow the full digitalization of the radio system which poses an important step towards the complete software description of RF signals proposed in SDR. Using digital signal processing techniques and the integration of the radio into a single digital chip, it is expected that high flexibility in these systems will be fundamental for the next generation of wireless networks. In addition, FPGA-based architectures take advantage of the high and heterogeneous processing power of modern FPGAs as well as their dynamic configurability capabilities needed for highly flexible radio transceivers.

关键词： field programmable gate arrays Pulse width modulation Radio frequency Receivers Baseband Radio transmitters RF signals

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Towards heterogeneous solvers for large-scale linear systems

Towards heterogeneous solvers for large-scale linear systems

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international conference on field programmable logic and applications

作者： Stylianos I. Venieris Grigorios Mingas Christos-Savvas Bouganis Department of Electrical and Electronic Engineering Imperial College London London UK

Applying Linear Regression to systems with a massive amount of observations, a scenario which is becoming increasingly common in the era of Big Data, poses major algorithmic and computational challenges. this paper proposes a novel high-performance FPGA-based architecture for large-scale Linear Regression problems as well as a heterogeneous system comprising the custom FPGA architecture, an enhanced GPU module and a multi-core CPU for addressing the aforementioned problem. the system adaptively assigns Linear Regression workloads to the three computing devices to minimise runtime. the device with the highest performance is chosen based on an analytical framework, as well as the workload's size and structure. A quantitative comparison with existing FPGA, GPU and multi-core CPU designs yields speed-ups of up to 18.07×, 32.67× and 25.84× respectively.

关键词： Graphics processing units field programmable gate arrays Computer architecture Digital signal processing Matrix decomposition Performance evaluation Algorithm design and analysis

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