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检索条件"任意字段=25th International Conference on Field Programmable Logic and Applications"

共 1842 条记录，以下是91-100 订阅

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Fitop-Trans: Maximizing Transformer Pipeline Efficiency through Fixed-Length Token Pruning on FPGA

Fitop-Trans: Maximizing Transformer Pipeline Efficiency thro...

引用

international conference on field programmable logic and applications

作者： Kejia Shi Manting Zhang Keqing Zhao Xiaoxing Wu Yang Liu Jun Yu Kun Wang School of Microelectronics Fudan University Shanghai China

ISBN: (数字)9798331530075

ISBN: (纸本)9798331530082

Recent years have witnessed Transformers emerge as a groundbreaking innovation in the Natural Language Processing (NLP) field. Unlike Recurrent Neural Network (RNN) models, Transformers process sequences in parallel, boosting accuracy for longer sequences. However, Transformers face challenges with extended processing time. this is particularly due to the requirement of padding inputs to match the longest sentence in a batch, thereby increasing computational demands. In this paper, we present Fitop-Trans, the first algorithm-hardware co-optimized framework using Fixed-Length Token Pruning strategy while deploying Transformers on FPGA. At the algorithmic level, we propose Fixed-Length Token Pruning. It is a novel pruning method which can maximize hardware efficiency in attention computation, aimed at eliminating unimportant tokens before the first layer. On the hardware side, a token selector is designed for Fixed-Length Token Pruning, which minimizes off-chip memory traffic. In addition, a partitionable Systolic Array (SA) is adopted, which is capable of handling varying input lengths and maximizing Digital Signal Processor (DSP) resource utilization. Furthermore, a scheduling module is designed to optimize hardware resource allocation and enhance pipeline attention throughput. Experimental results reveal that our hardware design on FPGA achieves a speedup of $580 \times$ and $6.39 \times$ in latency compared to Intel Xeon Gold CPU and NVIDIA GeForce RTX 3090.

关键词： Gold Recurrent neural networks Processor scheduling Pipelines Signal processing algorithms Transformers Hardware Natural language processing Resource management field programmable gate arrays

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Leveraging Dual Output LUTs with Pipelining for Efficient BCD to Binary Converter on FPGA

Leveraging Dual Output LUTs with Pipelining for Efficient BC...

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international conference on VLSI Design

作者： Santosh Kumar Ayan Palchaudhuri Department of Electronics & Communication Engineering School of Electrical and Computer Sciences Indian Institute of Technology Bhubaneswar Argul Khordha Odisha India

ISBN: (数字)9798331522445

ISBN: (纸本)9798331522452

Decimal operands expressed in BCD is often the convenient data format used in embedded systems and human-centric applications. For optimized arithmetic computation on hardware where binary arithmetic can be conveniently processed, input BCD operands should first be converted to binary. this paper explores the versatility of FPGA specific logic primitives, namely the dual output Look-Up Tables (LUTs) and carry chain for efficient realization of parallel and pipelined architectures to optimize throughput and resource utilization for BCD to binary conversion architectures. Primitive instantiation was adopted to ensure design optimization, which involved direct configuration of FPGA logic primitives. the utility ratio of the configured FPGA primitives was increased to extract the best performance. Experimental results demonstrate a good trade-off in speed and area for our proposed architectures when compared with existing designs. We have investigated multiple implementation variants for the addition tree, which serves as a crucial functional logic block in the converter design.

关键词： Embedded systems Computer architecture Very large scale integration throughput Table lookup logic field programmable gate arrays Adders Optimization Arithmetic

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Small Area Footprint FPGA Architecture for Approximate atan2(a, b) Algorithm 9

Small Area Footprint FPGA Architecture for Approximate atan2...

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9th IEEE Uttar Pradesh Section international conference on Electrical, Electronics and Computer Engineering, UPCON 2022

作者： Kumar, Bharat Sarawadekar, Kishor Dept. of Electronics Engineering Varanasi India

ISBN: (数字)9798350332506

ISBN: (纸本)9798350332506

Arctangent or inverse tangent function has numerous applications like gradient-based feature extraction, phase noise determination, range rate measurement etc. this paper presents a small area footprint hardware architecture for computing the arctangent of a complex number. the proposed method uses numerical approximation and LUTs used to improve the accuracy of the results obtained. Single-precision floating-point representation is used to implement the proposed design and the results demonstrate very good accuracy with an error of about ±0.0004 radian with 256×32 bits memory size. the proposed architecture is implemented on Nexys4 DDR FPGA board using Verilog and it operates at 19.8 MHz. Integrated logic Analyzer (ILA) is used to debug and validate the proposed design. Further, it is observed that results obtained with the proposed design are in agreement with the Matlab simulation results. © 2022 IEEE.

关键词： field programmable gate arrays (FPGA)

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A Software-programmable Neural Processing Unit for Graph Neural Network Inference on FPGAs

A Software-Programmable Neural Processing Unit for Graph Neu...

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international conference on field programmable logic and applications

作者： Taikun Zhang Andrew Boutros Sergey Gribok Kwadwo Boateng Vaughn Betz Department of Electrical and Computer Engineering University of Toronto Toronto ON Canada Programmable Solutions Group Intel Corporation

ISBN: (数字)9798331530075

ISBN: (纸本)9798331530082

Graph neural networks (GNNs) are a widely-used class of deep learning (DL) models for learning latent representations of graph-structured data for a variety of node/graph-level prediction tasks, some of which require real-time low latency inference. Most existing GNN accelerators rely on preprocessing input graphs on a host/embedded CPU to parallelize computations on different sub-graphs, making them unsuitable for real-time use cases. Others are extremely specialized streaming pipelines for only a specific type of GNN and therefore suffer from long FPGA bitstream compile times when the model is updated and cannot be used in applications that combine GNNs with other classes of DL models. In this work, we enhance the neural processing unit (NPU) FPGA overlay architecture, instruction set, and software stack to support a variety of GNN models. We achieve this without sacrificing the NPU flexibility; our enhanced NPU can be programmed purely through software to accelerate different GNNs or any of its originally supported DL workloads (e.g. MLPs, RNNs, GRUs, LSTMs). In addition, this flexibility enables our NPU software compiler to generate GNN kernels with different performance targets (throughput-optimized vs. latency-optimized) by exploiting different dimensions of compute parallelism on the same overlay architecture. Besides the flexibility benefits, our NPU implemented on an Intel Stratix 10 NX (14 nm) FPGA can process $7.8 \times$ more graphs per second at a similar latency on average compared to a state-of-the-art model-specific FPGA accelerator targeting real-time applications on an AMD Ultrascale+ same-generation FPGA. It also achieves 5.8 $\times$ higher throughput compared to an Nvidia RTX A6000 GPU (8 nm) and $2.6 \times$ lower latency than a state-of-the-art accelerator that combines CPU-based graph preprocessing with AMD Versal (7 nm) fabric and AI engine compute. Finally, we present a case study for using our enhanced NPU in real-time GNNbased multi-input

关键词： Computational modeling Data preprocessing Full stack Computer architecture throughput Graph neural networks Real-time systems Software Vectors field programmable gate arrays

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LORA: A Latency-Oriented Recurrent Architecture for GPT Model on Multi-FPGA Platform with Communication Optimization

LORA: A Latency-Oriented Recurrent Architecture for GPT Mode...

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international conference on field programmable logic and applications

作者： ZhenDong Zheng Qianyu Cheng Teng Wang Lei Gong Xianglan Chen Cheng Tang Chao Wang Xuehai Zhou School of Computer Science and Technology Suzhou Institute for Advanced Research University of Science and Technology of China

ISBN: (数字)9798331530075

ISBN: (纸本)9798331530082

Large Language Models (LLMs) have been widely deployed in data centers to provide various services, among which the most representative is the Generative Pre-trained Transformer (GPT). the GPT model has heavy memory and computing overhead, and its inference process has two stages with distinct computing characteristics: Prefill and Decode. Utilizing existing GPUs and FPGA accelerators to construct a platform for deploying GPT in data centers faces the challenges of needing more effective synchronization schemes or structures with higher computational intensity. this paper proposes LORA, a low latency end-to-end GPT acceleration platform utilizing multiple FPGAs. Firstly, we optimize the synchronization timing of the GPT model to reduce the computation and communication overhead. Secondly, we devise some efficient synchronization steps for specific layers of the GPT model that overlap part of the computation and communication delay to improve the latency of our platform. Finally, we deploy recurrent structures on each FPGA to accelerate the different stages of the GPT model. Implemented on the Xilinx Alveo U280 FPGAs, LORA achieves an average $11.1 \times$ speedup over NVIDIA V100 GPUs on the modern GPT-2 model. Compared to the existing multi-FPGA accelerator appliance, LORA shows performance improvements of up to $4 \times$ and $2.7 \times$ in the Prefill and Decode stages.

关键词： Data centers Computational modeling LoRa Prototypes Transformers Data models Synchronization Low latency communication field programmable gate arrays Optimization

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NeuraLUT: Hiding Neural Network Density in Boolean Synthesizable Functions

NeuraLUT: Hiding Neural Network Density in Boolean Synthesiz...

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international conference on field programmable logic and applications

作者： Marta Andronic George A. Constantinides Department of Electrical and Electronic Engineering Imperial College London UK

ISBN: (数字)9798331530075

ISBN: (纸本)9798331530082

field-programmable Gate Array (FPGA) accelerators have proven successful in handling latency- and resource-critical deep neural network (DNN) inference tasks. Among the most computationally intensive operations in a neural network (NN) is the dot product between the feature and weight vectors. thus, some previous FPGA acceleration works have proposed mapping neurons with quantized inputs and outputs directly to lookup tables (LUTs) for hardware implementation. In these works, the boundaries of the neurons coincide with the boundaries of the LUTs. We propose relaxing these boundaries and mapping entire sub-networks to a single LUT. As the sub-networks are absorbed within the LUT, the NN topology and precision within a partition do not affect the size of the lookup tables generated. therefore, we utilize fully connected layers with floating-point precision inside each partition, which benefit from being universal function approximators, but with rigid sparsity and quantization enforced between partitions, where the NN topology becomes exposed to the circuit topology. Although cheap to implement, this approach can lead to very deep NNs, and so to tackle challenges like vanishing gradients, we also introduce skip connections inside the partitions. the resulting methodology can be seen as training DNNs with a specific FPGA hardware-inspired sparsity pattern that allows them to be mapped to much shallower circuit-level networks, thereby significantly improving latency. We validate our proposed method on a known latency-critical task, jet substructure tagging, and on the classical computer vision task, digit classification using MNIST. Our approach allows for greater function expressivity within the LUTs compared to existing work, leading to up to $4.3 \times$ lower latency NNs for the same accuracy.

关键词： Training Quantization (signal) Neurons Artificial neural networks Tagging Vectors Table lookup Topology field programmable gate arrays Biological neural networks

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HASS: Hardware-Aware Sparsity Search for Dataflow DNN Accelerator

HASS: Hardware-Aware Sparsity Search for Dataflow DNN Accele...

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international conference on field programmable logic and applications

作者： Zhewen Yu Sudarshan Sreeram Krish Agrawal Junyi Wu Alexander Montgomerie-Corcoran Cheng Zhang Jianyi Cheng Christos-Savvas Bouganis Yiren Zhao Imperial College London UK University of Cambridge UK

ISBN: (数字)9798331530075

ISBN: (纸本)9798331530082

Deep Neural Networks (DNNs) excel in learning hierarchical representations from raw data, such as images, audio, and text. To compute these DNN models with high performance and energy efficiency, these models are usually deployed onto customized hardware accelerators. Among various accelerator designs, dataflow architecture has shown promising performance due to its layer-pipelined structure and its scalability in data *** weights and activations sparsity can further enhance memory storage and computation efficiency. However, existing approaches focus on exploiting sparsity in non-dataflow accelerators, which cannot be applied onto dataflow accelerators because of the large hardware design space introduced. As such, this could miss opportunities to find an optimal combination of sparsity features and hardware *** this paper, we propose a novel approach to exploit unstructured weights and activations sparsity for dataflow accelerators, using software and hardware co-optimization. We propose a Hardware-Aware Sparsity Search (HASS) to systematically determine an efficient sparsity solution for dataflow accelerators. Over a set of models, we achieve an efficiency improvement ranging from $1.3 \times$ to $4.2 \times$ compared to existing sparse designs, which are either non-dataflow or non-hardware-aware. Particularly, the throughput of MobileNetV3 can be optimized to 4895 images per second. HASS is open-source: https://***/Yu-Zhewen/HASS

关键词： Systematics Computational modeling Scalability Heuristic algorithms Memory management Artificial neural networks throughput Software logic Optimization

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Leveraging HBM2 for Accelerating k-mer Counting with oneAPI on FPGAs

Leveraging HBM2 for Accelerating k-mer Counting with oneAPI ...

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international conference on field programmable logic and applications

作者： Owen P. Lucas Alan D. George NSF SHREC Center ECE University of Pittsburgh Pittsburgh USA

ISBN: (数字)9798331530075

ISBN: (纸本)9798331530082

Counting substrings of an arbitrary length k (k-mers) is the single most time-consuming step of de novo genome sequencing. Sequencing machines generate large quantities of data $(\gt100$ s of GBs per genome), which need to be processed using frequent memory accesses into data structures considerably larger than available cache, leading to a memorybound runtime. Stemming from the gap between processor and memory speed, this bottleneck requires alternative architectures. Recent FPGA devices, equipped with on-chip High-Bandwidth Memory (HBM), enable custom architectures to employ high-capacity, high-bandwidth memory to address memory-bound tasks. this research investigates accelerating k-mers counting with one such device, the BittWare 520N-MX, a Stratix 10 FPGA with 16 GB of on-chip HBM2. the architecture was designed using Intel’s oneAPI, which enables high-level synthesis for FPGA programming. the accelerator architecture was able to leverage inherent parallelism in the algorithm via the multiple parallel hash functions, along with partitioning data structure across multiple memory banks, and employing multiple independent parallel processing pipelines on the device to maximize throughput. the accelerator achieved $42.67 \mathrm{M} \boldsymbol{k}$-mers per second, $2.80 \times$ more than the throughput-optimized CPU version and $4.31 \times$ more than the original CPU app. Despite this speedup, the architectures saw diminishing returns when attempting to incorporate additional HBM2 banks. OneAPI was able to achieve speedup over the CPU using the FPGA and emerging memory, but it’s somewhat limited in its current scaling capabilities.

关键词： Performance evaluation Hash functions Sequential analysis Pipelines Parallel processing logic gates throughput System-on-chip Kernel field programmable gate arrays

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DTrans: A Dataflow-transformation FPGA Accelerator with Nonlinear-operators fusion aiming for the Generative Model

DTrans: A Dataflow-transformation FPGA Accelerator with Nonl...

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international conference on field programmable logic and applications

作者： Xuanzheng Wang Shuo Miao Peng Qu Youhui Zhang Department of Computer Science and Technology Beijing National Research Center for Information Science and Technology Tsinghua University

ISBN: (数字)9798331530075

ISBN: (纸本)9798331530082

FPGA-based accelerators have emerged as an effective solution for GPT inference, given their inherent flexibility and capacity for domain-specific customization. However, the effective utilization of GPT has been hindered by two main obstacles: the unequal ratios between compute and memory access during the prefilling and generation stages, and the growing hardware resource requirements for nonlinear operations caused by longer text lengths and larger embedding dimensions. To address these challenges, we introduce DTrans, an FPGA accelerator specifically designed for GPT, which leverages nonlinear-operator fusion and a customized pipeline to efficiently handle long-input and long-generation tasks. We introduce a sequence-length-decoupled nonlinear operator design that enables in-place execution while preserving computational accuracy. Additionally, we employ a customized pipeline design that utilizes a two-level alternating input pipeline mapping for long-input tasks to alleviate the overhead associated with residual computation and on-chip buffers. Furthermore, for long-token generation tasks, our pipeline overlaps computational delays in operations such as Softmax and layer normalization with matrix operations. We also propose a novel two-stage dataflow transformation strategy that adopts different reuse strategies for the prefilling and generating stages with different computational/memory access characteristics. Our comparative analyses reveal that DTrans outperforms the GPU(V100) in terms of throughput and energy efficiency, achieving improvements of $11.99 \times$ and $11.7 \times$, respectively. When compared with state-of-the-art GPT inference accelerators, DTrans demonstrates more than $5.64 \times$ and $5.22 \times$ enhancements in these metrics.

关键词： Measurement Accuracy Pipelines Memory management throughput Energy efficiency System-on-chip Delays logic field programmable gate arrays

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SDA: Low-Bit Stable Diffusion Acceleration on Edge FPGAs

SDA: Low-Bit Stable Diffusion Acceleration on Edge FPGAs

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international conference on field programmable logic and applications

作者： Geng Yang Yanyue Xie Zhong Jia Xue Sung-En Chang Yanyu Li Peiyan Dong Jie Lei Weiying Xie Yanzhi Wang Xue Lin Zhenman Fang Xidian University Simon Fraser University Northeastern University University of Technology Sydney

ISBN: (数字)9798331530075

ISBN: (纸本)9798331530082

this paper introduces SDA, the first effort to adapt the expensive stable diffusion (SD) model for edge FPGA deployment. First, we apply quantization-aware training to quantize its weights to 4 -bit and activations to 8 -bit ($W 4 A 8$) with a negligible accuracy loss. Based on that, we propose a high-performance hybrid systolic array (hybridSA) architecture that natively executes convolution and attention operators across varying quantization bit-widths (e.g., $W 4 A 8$ and all 8 -bit $Q K^{T} V$ in attention). To improve computational efficiency, hybridSA integrates diverse DSP packing techniques into hybrid weightstationary and output-stationary dataflows that are optimized for convolution and attention. It also supports flexible dataflow transitions to address the distinct demands of its output sequence by subsequent nonlinear operators. Moreover, we observe that nonlinear operators become the new performance bottleneck after the acceleration of convolution and attention, and offload them onto the FPGA as well. To reduce the latency of each nonlinear operator, we pipeline its own execution at a fine granularity. To minimize the resource utilization of nonlinear operators, we carefully balance their execution with hybridSA in a coarse-grained pipeline. Experimental results demonstrate that our low-bit ($W 4 A 8$) SDA accelerator on the embedded AMDXilinx ZCU102 FPGA achieves a speedup of $97.3 \times$ (which takes about $\mathrm{2 . 1}$ minutes for one SD inference), compared to the original SD-v1.5 model on the ARM Cortex-A53 CPU (which takes about 3.5 hours for one SD inference). Our SDA project is open sourced here: https://***/Michaela1224/SDA_code.

关键词： Training Quantization (signal) Convolution Pipelines Computer architecture Systolic arrays Computational efficiency Resource management logic field programmable gate arrays

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