检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

1,813 篇 会议
30 篇 期刊文献
5 册 图书

馆藏范围

1,848 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

1,203 篇 工学
- 1,020 篇 计算机科学与技术...
- 707 篇 软件工程
- 388 篇 电气工程
- 186 篇 电子科学与技术（可...
- 62 篇 信息与通信工程
- 60 篇 控制科学与工程
- 26 篇 机械工程
- 25 篇 动力工程及工程热...
- 24 篇 建筑学
- 23 篇 仪器科学与技术
- 16 篇 土木工程
- 14 篇 生物工程
- 11 篇 核科学与技术
- 10 篇 材料科学与工程（可...
- 9 篇 光学工程
- 8 篇 生物医学工程（可授...
- 8 篇 安全科学与工程
- 6 篇 化学工程与技术
- 6 篇 交通运输工程
146 篇 理学
- 97 篇 数学
- 33 篇 物理学
- 16 篇 生物学
- 14 篇 系统科学
- 10 篇 统计学（可授理学、...
- 6 篇 化学
52 篇 管理学
- 39 篇 管理科学与工程(可...
- 17 篇 工商管理
- 15 篇 图书情报与档案管...
14 篇 法学
- 12 篇 社会学
9 篇 经济学
- 9 篇 应用经济学
8 篇 医学
6 篇 农学
4 篇 军事学
2 篇 教育学

主题

817 篇 field programmab...
670 篇 field programmab...
271 篇 hardware
155 篇 computer archite...
119 篇 logic gates
111 篇 table lookup
94 篇 clocks
83 篇 throughput
78 篇 random access me...
72 篇 routing
71 篇 acceleration
71 篇 software
66 篇 optimization
63 篇 kernel
62 篇 delays
52 篇 registers
52 篇 logic
49 篇 switches
46 篇 algorithm design...
45 篇 computational mo...

机构

15 篇 univ toronto dep...
9 篇 department of co...
9 篇 imperial coll lo...
8 篇 ecole polytech f...
7 篇 univ british col...
7 篇 school of comput...
7 篇 brigham young un...
7 篇 imperial coll lo...
7 篇 tokyo inst techn...
6 篇 univ tsukuba tsu...
6 篇 university of ch...
6 篇 department of el...
6 篇 univ warwick sch...
6 篇 xilinx inc san j...
5 篇 univ manchester ...
5 篇 department of el...
5 篇 univ toronto dep...
5 篇 swiss fed inst t...
5 篇 xilinx inc 2100 ...
5 篇 altera corp san ...

作者

33 篇 luk wayne
21 篇 maruyama tsutomu
16 篇 wayne luk
16 篇 koch dirk
12 篇 wilton steven j....
12 篇 betz vaughn
12 篇 ienne paolo
11 篇 fahmy suhaib a.
11 篇 cheung peter y. ...
10 篇 vaughn betz
9 篇 constantinides g...
8 篇 suhaib a. fahmy
8 篇 prasanna viktor ...
8 篇 chow paul
8 篇 glesner manfred
8 篇 amano hideharu
8 篇 akash kumar
7 篇 kapre nachiket
7 篇 alonso gustavo
7 篇 hutchings brad

语言

1,823 篇 英文
25 篇 其他
1 篇 中文

检索条件"任意字段=25th International Conference on Field Programmable Logic and Applications"

共 1848 条记录，以下是991-1000 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

An efficient and flexible host-FPGA PCIe communication library

An efficient and flexible host-FPGA PCIe communication libra...

引用

international conference on field programmable logic and applications

作者： Jian Gong Tao Wang Jiahua Chen Haoyang Wu Fan Ye Songwu Lu Jason Cong Peking University Beijing Beijing CN

A high-performance interconnection between a host processor and FPGA accelerators is in much demand. Among various interconnection methods, a PCIe bus is an attractive choice for loosely coupled accelerators. Because there is no standard host-FPGA communication library, FPGA developers have to write significant amounts of PCIe related code at both the FPGA side and the host processor side. A high-performance host-FPGA PCIe communication library holds the key to broadening the use of FPGA accelerators. In this paper we target efficiency and flexibility as two important features in such a library. We discuss the challenges in providing these features, and present our solution to these challenges. We propose EPEE, an efficient and flexible host-FPGA PCIe communication library and describe its design. We implemented EPEE in various generations of Xilinx FPGAs with up to 26.24 Gbps half-duplex and 43.02 Gbps full-duplex aggregate throughput in the PCIe Gen2 X8 mode; these are at the best utilization levels that a host-FPGA PCIe library can achieve. the EPEE library has been integrated into four different FPGA applications with different data usage patterns in various institutes.

关键词： field programmable gate arrays Libraries Software Hardware throughput IP networks Registers

来源：评论

学校读者我要写书评

暂无评论

Patra: Parallel tree-reweighted message passing architecture

Patra: Parallel tree-reweighted message passing architecture

引用

international conference on field programmable logic and applications

作者： Wenlai Zhao Haohuan Fu Guangwen Yang Wayne Luk Ministry of Education Key Laboratory for Earth System Modeling Tsinghua University Tsinghua National Laboratory for Information Science and Technology (TNList) Department of Computing Imperial College London

Maximum a posteriori probability inference algorithms for Markov Random field are widely used in many applications, such as computer vision and machine learning. Sequential tree-reweighted message passing (TRW-S) is an inference algorithm which shows good quality in finding optimal solutions. However, the performance of TRW-S in software cannot meet the requirements of many real-time applications, due to the sequential scheme and the high memory, bandwidth and computational costs. this paper proposes Patra, a novel parallel tree-reweighted message passing architecture, which involves a fully pipelined design targeting FPGA technology. We build a hybrid CPU/FPGA system to test the performance of Patra for stereo matching. Experimental results show that Patra provides about 100 times faster than a software implementation of TRW-S, and 12 times faster than a GPU-based message passing algorithm. Compared with an existing design in four FPGAs, we can achieve 2 times speedup in a single FPGA. Moreover, Patra can work at video rate in many cases, such as a rate of 167 frame/sec for a standard stereo matching test case, which makes it promising for many real-time applications.

关键词： field programmable gate arrays Message passing Algorithm design and analysis Bandwidth Random access memory Accuracy Vectors

来源：评论

学校读者我要写书评

暂无评论

High throughput channel tracking for JTRS wireless channel emulation

High throughput channel tracking for JTRS wireless channel e...

引用

international conference on field programmable logic and applications

作者： Dajung Lee Janarbek Matai Brad Weals Ryan Kastner Electrical and Computer Engineering Computer Science and Engineering University of California San Diego Toyon Research Corporation

Testing and verifying wireless systems in a real world environments is a challenging but an important problem. this is particular true for the Joint Tactical Radio System (JTRS) where the modulation techniques are optimized towards environments that are difficult to reproduce (e.g., ship to plane, plane to satellite communications). Such cases necessitate a wireless channel emulator to facilitate testing in the laboratory as the protocols are being developed. Furthermore, the increasing complexity of communications protocols and highly variable network scenarios force the channel emulator to support an accurate and complicated channel model that can scale to handle a large number of radios that operate across a wide frequency spectrum. We developed a unique channel impairment emulator prototype to meet these requirements. It maximizes the scalability and performance, operating in a frequency range of 2 MHz to 2 GHz. Moreover, our emulator design accommodates radio operation that use unknown frequency hopping techniques, which is increasingly common in JTRS systems. this key feature to this system is a high throughput channel tracker module that handles high bandwidth intermediate frequency (IF) signals while providing the scalability to handle a large number of channels.

关键词： throughput Wireless communication field programmable gate arrays Optimization Hardware Clocks Radio frequency

来源：评论

学校读者我要写书评

暂无评论

A scalable, serially-equivalent, high-quality parallel placement methodology suitable for modern multicore and GPU architectures

A scalable, serially-equivalent, high-quality parallel place...

引用

international conference on field programmable logic and applications

作者： Christian Fobel Gary Grewal Deborah Stacey School of Computer Science University of Guelph Guelph Ontario Canada

Placement and routing run-times continue to dominate the automated FPGA design flow. As the size of FPGA architectures continue to grow exponentially, it remains critical to develop parallel tools for FPGA design where the amount of exposed concurrent work scales with the size of the designs to be synthesized. In this paper, we propose a novel algorithm for parallel placement, based on simulated annealing, where the amount of parallel work directly scales with the size of the net-list to be placed. Our approach concurrently evaluates and conditionally applies very large sets of non-conflicting swaps using common parallel computing primitives, including stream compaction, category reduction, and sort. While our design is suitable for targeting all modern parallel computing platforms, we present results from our implementation which targets NVIDIA's CUDA platform, where we achieve a mean speed-up of 19x over VPR with post-routing critical-path-delay and wire-length quality that matches or exceeds VPR. We believe that this work is an important step towards the development of a scalable, high-quality placement tool.

关键词： field programmable gate arrays Annealing Computational modeling Instruction sets Computer architecture Educational institutions Indexes

来源：评论

学校读者我要写书评

暂无评论

Compiling text analytics queries to FPGAs

Compiling text analytics queries to FPGAs

引用

international conference on field programmable logic and applications

作者： Raphael Polig Kubilay Atasu Heiner Giefers Laura Chiticariu IBM Research - Zurich Rueschlikon Switzerland IBM Research - Almaden San Jose CA USA

Extracting information from unstructured text data is a compute-intensive task. the performance of general-purpose processors cannot keep up with the rapid growth of textual data. therefore we discuss the use of FPGAs to perform large scale text analytics. We present a framework consisting of a compiler and an operator library capable of generating a Verilog processing pipeline from a text analytics query specified in the annotation query language AQL. the operator library comprises a set of configurable modules capable of performing relational and extraction tasks which can be assembled by the compiler to represent a full annotation operator graph. Leveraging the nature of text processing we show that most tasks can be performed in an efficient streaming fashion. We evaluate the performance, power consumption and hardware utilization of our approach for a set of different queries compiled to a Stratix IV FPGA. Measurements show an up to 79 times improvement of document-throughput over a 64 threaded software implementation on a POWER7 server. Moreover the accelerated system's energy efficiency is up to 85 times better.

关键词： Hardware field programmable gate arrays Software Database languages Libraries Hardware design languages Acceleration

来源：评论

学校读者我要写书评

暂无评论

Energy-aware SQL query acceleration through FPGA-based dynamic partial reconfiguration

Energy-aware SQL query acceleration through FPGA-based dynam...

引用

international conference on field programmable logic and applications

作者： Andreas Becher Florian Bauer Daniel Ziener Jürgen Teich Hardware/Software Co-Design Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU) Germany

In this paper, we propose an approach for energy-aware FPGA-based query acceleration for databases on embedded devices. After the analysis of an incoming query, a query-specific hardware accelerator is generated on-the-fly and loaded on the FPGA for subsequent query execution using partial dynamic reconfiguration. For each SQL query operation, a pre-synthesized partial bitstream implementation exists in a module library. this library includes modules for all major SQL operations like restrictions, aggregations, as well as more complex operations such as join and sort. the implementation of this flexible FPGA-based query accelerator approach on the embedded low-energy system-on-chip (SoC) platform Xilinx Zynq shows SQL query processing speeds comparable to high-end database servers, however, at a much lower energy consumption. Indeed, provided experimental results give evidence that the proposed architecture may reduce the amount of consumed energy to just 5% of the energy needed of an in-memory database system running on an x86-based server at equal throughput for respective benchmarks.

关键词： field programmable gate arrays Acceleration Hardware throughput Libraries Switches Databases

来源：评论

学校读者我要写书评

暂无评论

Simplification and hardware implementation of the feature descriptor vector calculation in the SIFT algorithm

Simplification and hardware implementation of the feature de...

引用

international conference on field programmable logic and applications

作者： P. Leyva G. Doménech-Asensi J. Garrigós J. Illade-Quinteiro V. M. Brea P. López D. Cabello Dpto. de Electrónica Tec. de Computadoras y Proyectos Universidad Politécnica de Cartagena Cartagena Spain Centro de Inv. en Tecnoloxías da Información (CITIUS) University of Santiago de Compostela Santiago de Compostela Spain

this paper proposes a hardware implementation to speed up the calculation of the feature descriptor vector in the Scale-Invariant Feature Transform (SIFT) algorithm. the proposed architecture, which improves conventional solutions based on embedded processors or other hardware/software co-designs, computes a feature descriptor vector of 27 elements from a keypoint neighborhood of 15×15 pixels. this process comprises several steps, including complex operations such as vector normalization operations. the paper compares two different implementations: one being time-optimized and the other memory-optimized. Both approaches require 649 and 874 clock cycles respectively for a single feature vector calculation (6.49 μs and 8.74 μs for a 100 MHz FPGA).

关键词： Vectors Histograms Hardware Topology Feature extraction Computer architecture field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

Adaptive scalable SVD unit for fast processing of large LSE problems

Adaptive scalable SVD unit for fast processing of large LSE ...

引用

international conference on Application Specific Systems (ASAP), Architectures and Processors

作者： Iñaki Bildosola Unai Martinez-Corral Koldo Basterretxea Grupo de Diseño en Electrónica Digital (GDED) University of the Basque Country (UPV/EHU) Bilbao Spain Dept. Electronics Technology University of the Basque Country (UPV/EHU) Bilbao Spain

Singular Value Decomposition (SVD) is a key linear algebraic operation in many scientific and engineering applications. In particular, many computational intelligence systems rely on machine learning methods involving high dimensionality datasets that have to be fast processed for real-time adaptability. In this paper we describe a practical FPGA (field programmable Gate Array) implementation of a SVD processor for accelerating the solution of large LSE problems. the design approach has been comprehensive, from the algorithmic refinement to the numerical analysis to the customization for an efficient hardware realization. the processing scheme rests on an adaptive vector rotation evaluator for error regularization that enhances convergence speed with no penalty on the solution accuracy. the proposed architecture, which follows a data transfer scheme, is scalable and based on the interconnection of simple rotations units, which allows for a trade-off between occupied area and processing acceleration in the final implementation. this permits the SVD processor to be implemented both on low-cost and highend FPGAs, according to the final application requirements.

关键词： Accuracy Jacobian matrices Convergence Computer architecture Algorithm design and analysis field programmable gate arrays Matrix decomposition

来源：评论

学校读者我要写书评

暂无评论

Tile-based bottom-up compilation of custom mesh-of-functional-units FPGA overlays

Tile-based bottom-up compilation of custom mesh-of-functiona...

引用

international conference on field programmable logic and applications

作者： Davor Capalija Tarek S. Abdelrahman Department of Electrical and Computer Engineering University of Toronto Toronto ON Canada

Mesh-of-functional-units (mesh-of-FUs) overlays can deliver high-performance because they expose the massively parallel FPGA fabric and have the ability to be customized for different applications. However, a key challenge is how to quickly compile a number of custom mesh-of-FUs overlays to FPGA fabric such that they achieve high f MAX and scale to large mesh sizes. We propose a tile-based bottom-up CAD flow that utilizes the hierarchical physical design techniques of partitioning and floorplanning. Our flow partitions the overlay circuit into tiles, groups of adjacent overlay cells, and then compiles the tiles to a rectangular coarse-grain floorplan. Independent compilation of tiles is made possible by inserting complementary elastic buffers on inter-tile paths to ensure that these paths are not a bottleneck for f MAX . As a result, an overlay can be formed by only “stitching” a set of pre-compiled *** show that compared to the flat flow, our bottom-up flow results in higher f MAX that degrades little with increasing overlay size. Further, our flow can generate a library of pre-compiled tiles that can be reused - it can stitch a set of library tiles into a new overlay in only 35 minutes. It also allows a divide-and-conquer overlay compilation flow by compiling its tiles in parallel on multiple machines.

关键词： field programmable gate arrays Design automation Registers Libraries Ports (Computers) Layout Digital signal processing

来源：评论

学校读者我要写书评

暂无评论

Identifying and placing heterogeneously-sized cluster groupings based on FPGA placement data

Identifying and placing heterogeneously-sized cluster groupi...

引用

international conference on field programmable logic and applications

作者： Farnaz Gharibian Lesley Shannon Peter Jamieson School of Engineering Science Simon Fraser University Department of Electrical and Computer Engineering Miami University

field programmable Gate Arrays (FPGAs) CAD flow run-time has increased due to the rapid growth in size of designs and FPGAs. Researchers are trying to find new ways to improve compilation time without degrading design performance. In this paper, we present a novel approach that identifies tightly grouped FPGA logic blocks and then uses this information during circuit placement. Our approach is an orthogonal optimization applicable in incremental design and physical optimization, and reduces placement run-time. Specifically, we present a new algorithm that analyzes designs post-placement to extract medium-grained super-clusters that consist of two to seventeen clusters, which we call “gems”. We modified VPR's simulated annealing placement algorithm to place our mixture of gems and clusters. Our new “Singularity Annealing” algorithm first crushes each cluster grouping into a “singularity” (treated as a single cluster). then, the Singularity Annealer is run over this condensed circuit to obtain an initial placement, followed by an expansion of the singularities. Finally, we run a second low-temperature annealing phase on the entire expanded circuit. Our results show that our system reduces placement run-time on average by 17% while maintains the designs critical path delay, and increases designs channel width, and wirelength by 2% and 6.3%, respectively. We have also presented a test case to show the re-usability of gems in an incremental design example.

关键词： field programmable gate arrays Benchmark testing Clustering algorithms Algorithm design and analysis Design automation Delays Annealing

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共185页 << < 96 97 98 99 100 101 102 103 104 105 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：