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检索条件"任意字段=25th International Conference on Field Programmable Logic and Applications"

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Identifying and placing heterogeneously-sized cluster groupings based on FPGA placement data

Identifying and placing heterogeneously-sized cluster groupi...

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international conference on field programmable logic and applications

作者： Farnaz Gharibian Lesley Shannon Peter Jamieson School of Engineering Science Simon Fraser University Department of Electrical and Computer Engineering Miami University

field programmable Gate Arrays (FPGAs) CAD flow run-time has increased due to the rapid growth in size of designs and FPGAs. Researchers are trying to find new ways to improve compilation time without degrading design performance. In this paper, we present a novel approach that identifies tightly grouped FPGA logic blocks and then uses this information during circuit placement. Our approach is an orthogonal optimization applicable in incremental design and physical optimization, and reduces placement run-time. Specifically, we present a new algorithm that analyzes designs post-placement to extract medium-grained super-clusters that consist of two to seventeen clusters, which we call “gems”. We modified VPR's simulated annealing placement algorithm to place our mixture of gems and clusters. Our new “Singularity Annealing” algorithm first crushes each cluster grouping into a “singularity” (treated as a single cluster). then, the Singularity Annealer is run over this condensed circuit to obtain an initial placement, followed by an expansion of the singularities. Finally, we run a second low-temperature annealing phase on the entire expanded circuit. Our results show that our system reduces placement run-time on average by 17% while maintains the designs critical path delay, and increases designs channel width, and wirelength by 2% and 6.3%, respectively. We have also presented a test case to show the re-usability of gems in an incremental design example.

关键词： field programmable gate arrays Benchmark testing Clustering algorithms Algorithm design and analysis Design automation Delays Annealing

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Privacy preserving large scale DNA read-mapping in MapReduce framework using FPGAs

Privacy preserving large scale DNA read-mapping in MapReduce...

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international conference on field programmable logic and applications

作者： Lei Xu Hanyee Kim Xi Wang Weidong Shi Taeweon Suh University of Houston United States Korea University Republic of Korea

Read-mapping, i.e., finding certain patterns in a long DNA sequence, is an important operation for molecular biology. It is widely used in a variety of biological analyses including SNP discovery, genotyping and personal genomics. As next-generation DNA sequencing machines are generating an enormous amount of sequence data, it is a good choice to implement the read-mapping algorithm in the MapReduce framework and outsource the computation to the cloud. Data privacy becomes a big concern in this situation as DNA sequences are very sensitive. In response, encryption may be used to protect the data. However, it is very difficult for the cloud to process cipher texts. In the MapReduce framework, even if values (data to be processed) may be protected by encryption, keys cannot be encrypted using sematic secure encryption schemes as it will affect the MapReduce scheduling mechanism. But if no protection is utilized, attackers may extract useful information from unprotected keys. We propose a solution that can securely outsource read-mapping computations in the MapReduce framework by leveraging inherent tamper resistant properties of FPGAs. We also provide a method to protect the keys generated in this process. We implement our solution using FPGAs and apply it to some data sets. the security evaluation and experimental results show that with this method, DNA sequence privacy is well protected, and the extra cost is acceptable.

关键词： field programmable gate arrays Encryption Kernel Privacy Cloud computing

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A dynamically adaptable bus architecture for trading-off among performance, consumption and dependability in Cyber-Physical Systems

A dynamically adaptable bus architecture for trading-off amo...

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international conference on field programmable logic and applications

作者： J. Valverde A. Rodriguez J. Camarero A. Otero J. Portilla E. de la Torre T. Riesgo Centro de Electrónica Industrial - CEI Universidad Politécnica de Madrid Madrid Spain

Cyber-Physical Systems need to handle increasingly complex tasks, which additionally, may have variable operating conditions over time. therefore, dynamic resource management to adapt the system to different needs is required. In this paper, a new bus-based architecture, called ARTICo 3 , which by means of Dynamic Partial Reconfiguration, allows the replication of hardware tasks to support module redundancy, multi-thread operation or dual-rail solutions for enhanced side-channel attack protection is presented. A configuration-aware data transaction unit permits data dispatching to more than one module in parallel, or provide coalesced data dispatching among different units to maximize the advantages of burst transactions. the selection of a given configuration is application independent but context-aware, which may be achieved by the combination of a multi-thread model similar to the CUDA kernel model specification, combined with a dynamic thread/task/kernel scheduler. A multi-kernel application for face recognition is used as an application example to show one scenario of the ARTICo 3 architecture.

关键词： Computer architecture Kernel Graphics processing units field programmable gate arrays Hardware Acceleration Fault tolerance

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An empirical evaluation of High-Level Synthesis languages and tools for database acceleration

An empirical evaluation of High-Level Synthesis languages an...

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international conference on field programmable logic and applications

作者： Oriol Arcas-Abella Geoffrey Ndu Nehir Sonmez Mohsen Ghasempour Adrià Armejach Javier Navaridas Wei Song John Mawer Adrián Cristal Mikel Luján Universitat Politècnica de Catalunya BarcelonaTech (UPC) Spain School of Computer Science University of Manchester Manchester United Kingdom Barcelona Supercomputing Center (BSC) Barcelona Spain Universitat Politècnica de Catalunva BarcelonaTech (UPC) Barcelona Spain Centro Superior de Investigaciones Científicas (IIIA-CSIC) Spain

High Level Synthesis (HLS) languages and tools are emerging as the most promising technique to make FPGAs more accessible to software developers. Nevertheless, picking the most suitable HLS for a certain class of algorithms depends on requirements such as area and throughput, as well as on programmer experience. In this paper, we explore the different trade-offs present when using a representative set of HLS tools in the context of Database Management Systems (DBMS) acceleration. More specifically, we conduct an empirical analysis of four representative frameworks (Bluespec SystemVerilog, Altera OpenCL, LegUp and Chisel) that we utilize to accelerate commonly-used database algorithms such as sorting, the median operator, and hash joins. through our implementation experience and empirical results for database acceleration, we conclude that the selection of the most suitable HLS depends on a set of orthogonal characteristics, which we highlight for each HLS framework.

关键词： Hardware field programmable gate arrays Sorting Probes Databases Hardware design languages Acceleration

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Dataflow acceleration of Krylov subspace sparse banded problems

Dataflow acceleration of Krylov subspace sparse banded probl...

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international conference on field programmable logic and applications

作者： Pavel Burovskiy Stephen Girdlestone Craig Davies Spencer Sherwin Wayne Luk Department of Computing Imperial College London Department of Aeronautics Imperial College London Maxeler Technologies

Most of the efforts in the FPGA community related to sparse linear algebra focus on increasing the degree of internal parallelism in matrix-vector multiply kernels. We propose a parametrisable dataflow architecture presenting an alternative and complementary approach to support acceleration of banded sparse linear algebra problems which benefit from building a Krylov subspace. We use banded structure of a matrix A to overlap the computations Ax, A 2 x, ..., A k x by building a pipeline of matrix-vector multiplication processing elements (PEs) each performing A i x. Due to on-chip data locality, FLOPS rate sustainable by such pipeline scales linearly with k. Our approach enables trade-off between the number k of overlapped matrix power actions and the level of parallelism in a PE. We illustrate our approach for Google PageRank computation by power iteration for large banded single precision sparse matrices. Our design scales up to 32 sequential PEs with floating point accumulation and 80 PEs with fixed point accumulation on Stratix V D8 FPGA. With 80 single-pipe fixed point PEs clocked at 160Mhz, our design sustains 12.7 GFLOPS.

关键词： Vectors Sparse matrices Computer architecture Pipelines System-on-chip Random access memory field programmable gate arrays

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Hardware accelerated novel optical de novo assembly for large-scale genomes

Hardware accelerated novel optical de novo assembly for larg...

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international conference on field programmable logic and applications

作者： Pingfan Meng Matthew Jacobsen Motoki Kimura Vladimir Dergachev thomas Anantharaman Michael Requa Ryan Kastner University of California San Diego La Jolla CA US BioNano Genomics 9640 Towne Centre Dr. #100 San Diego CA 92121 USA

De novo assembly is a widely used methodology in bioinformatics. However, the conventional short-read based de novo assembly is incapable of reliably reconstructing the large-scale structures of human genomes. Recently, a novel optical label based technology has enabled reliable large-scale de novo assembly. Despite its advantage in large-scale genome analysis, this new technology requires a more computationally intensive alignment algorithm than its conventional counterpart. For example, the run-time of reconstructing a human genome is on the order of 10; 000 hours on a sequential CPU. therefore, in order to practically apply this new technology in genome research, accelerated approaches are desirable. In this paper, we present three different accelerated approaches, multi-core CPU, GPU and FPGA. Against the sequential software baseline, our multi-core CPU design achieved a 8.4× speedup while the GPU and FPGA designs achieved 13.6× and 115× speedups respectively. We also reveal the insights of the design space exploration of this new assembly algorithm on these three different devices by comparing the results.

关键词： Graphics processing units Assembly Acceleration Genomics Instruction sets field programmable gate arrays Kernel

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A fast and scalable FPGA damage diagnostic service for R3TOS using BIST cloning technique

A fast and scalable FPGA damage diagnostic service for R3TOS...

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international conference on field programmable logic and applications

作者： Ali Ebrahim Tughrul Arslan Xabier Iturbe School of Engineering The University of Edinburgh Edinburgh Scotland UK Embedded System-on-Chip Group IKERLAN-IK4 Research Basque Country Spain

this paper presents a new technique to be used in the context of reconfigurable computing to accelerate the online diagnosis of permanent damage on Xilinx FPGAs using Built-In Self Tests (BISTs). Detecting and locating permanently damaged resources with precision is central to keep the system implemented on the FPGA flawless at all times; i.e. upcoming hardware tasks are mapped to available functional resources, circumventing the use of the damaged ones. the proposed diagnostic technique exploits the Multiple Frame Write (MFW) feature available in Xilinx FPGAs to “clone” (i.e. replicate) a single basic BIST circuit along arbitrarily sized and shaped areas on the FPGA without incurring large time overheads. Hence, the proposed technique allows for creating at runtime on-demand tailored BIST circuits to satisfy any diagnosis requirements that may rise up. Moreover, the proposed solution allows for saving memory in the system as it only requires storing basic BIST circuits. Finally, the paper presents a diagnostic service for a Reliable Reconfigurable Real-Time Operating System (R3TOS) that is based on the BIST cloning technique and works in cooperation with the R3TOS fault-handling and recovery mechanisms.

关键词： Built-in self-test field programmable gate arrays Table lookup Circuit faults Cloning Hardware Shape

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Trade-offs and progressive adoption of FPGA acceleration in network traffic monitoring

Trade-offs and progressive adoption of FPGA acceleration in ...

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international conference on field programmable logic and applications

作者： Lukáš Kekely Viktor Puš Pavel Benáček Jan Kořenek CESNET Prague Czech Republic CESNET a. l. e. Zikova 4 160 00 Prague Czech Republic Faculty of Information Technology Brno University of Technology Brno Czech Republic

Current hardware acceleration cores for network traffic processing are often well optimized for one particular task and therefore provide high level of hardware acceleration. But for many applications, such as network traffic monitoring and security, it is also necessary to achieve rapid development cycle to provide fast response to security *** propose and evaluate a new concept of hardware acceleration for flexible flow-based network traffic monitoring with support of application protocol analysis. the concept is called Software Defined Monitoring (SDM) and it relies on a configurable hardware accelerator implemented in FPGA, coupled with smart monitoring tasks running as software on general CPU. the monitoring tasks in the software control the level of detail and type of information retained during the hardware processing. this arrangement allows rapid application prototyping in the software, followed by further shifting of the timing critical parts of the processing to the hardware accelerator. the concept is proposed with the scalability in mind, therefore it is suitable for different FPGA based platforms ranging from embedded single-chip solutions (such as Zynq or CycloneV) to high-speed backbone network monitoring boxes. Our pilot high-speed implementation using FPGA acceleration board in a commodity server performs a 100Gb/s flow traffic measurement augmented by a selected application protocol analysis.

关键词： Software Monitoring Hardware field programmable gate arrays Acceleration Protocols Security

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Caching memcached at reconfigurable network interface

Caching memcached at reconfigurable network interface

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international conference on field programmable logic and applications

作者： Eric S. Fukuda Hiroaki Inoue Takashi Takenaka Dahoo Kim Tsunaki Sadahisa Tetsuya Asai Masato Motomura Graduate School of Information Science and Technology Hokkaido University Sapporo Japan NEC Corporation Nakahara-ku Kawasaki Kanagawa Japan

Memcached is a technology that improves response speed of web servers by caching data on DRAMs in distributed servers. In order to achieve higher performance, memcached has been evaluated on various platforms. Among them, FPGA seems to be the most efficient platform to run memcached, and several research groups are trying to achieve higher throughput with it. However, it is difficult to utilize a large amount of memory (several dozen gigabytes) with an FPGA. Some groups are trying to solve this problem by using an embedded CPU for memory allocation and another group is employing an SSD. Unlike other approaches that try to replace memcached itself on FPGAs, our approach augments the software memcached running on the host CPU by caching its data and some operations at the FPGA-equipped network interface card (NIC) mounted on the server. the locality of memcached data enables the FPGA NIC to have a fairly high hit rate with a smaller memory. We first explore the cache parameters by software simulations and estimate the effectiveness of our approach, and then prototype a system to prove its effectiveness. through our evaluation with YCSB, a standard key-value store (KVS) benchmarking tool, we estimate that the latency improved by an order of magnitude over software memcached running on a high performance CPU.

关键词： field programmable gate arrays Random access memory Web servers throughput Facebook Hardware

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Analyzing the energy-efficiency of dense linear algebra kernels by power-profiling a hybrid CPU/FPGA system

Analyzing the energy-efficiency of dense linear algebra kern...

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international conference on Application Specific Systems (ASAP), Architectures and Processors

作者： Heiner Giefers Raphael Polig Christoph Hagleitner IBM Research - Zurich

It has been shown that FPGA accelerators can outperform pure CPU systems for highly parallel applications and they are considered as a power-efficient alternative to software programmable processors. However, when using FPGA accelerator cards in a server environment multiple sources of power consumption have to get taken into account in order to rate the systems energy-efficiency. In this paper we study the energy-efficiency of a hybrid CPU/FPGA system for a dense linear algebra kernel. We present an FPGA GEMM accelerator architecture that can be tailored to various data types. the performance and energy consumption is compared against tuned, multi-threaded GEMM functions running on the host CPU. We measure the power consumption with internal current/voltage sensors and break down the power draw to the systems components in order to classify the energy consumed by the processor cores, the memory, the I/O bus system and the FPGA card. Our experimental results show that the FPGA-accelerated DGEMM is less energy-efficient than a multi-threaded software implementation with respect to the full systems power consumption, but the most efficient choice when only the dynamic parts of the power are factored in.

关键词： field programmable gate arrays Power demand Kernel Vectors Adders Computer architecture Servers

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