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检索条件"任意字段=25th International Conference on Field Programmable Logic and Applications"

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An approach of processor core customization for stencil computation

An approach of processor core customization for stencil comp...

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international conference on Application Specific Systems (ASAP), Architectures and Processors

作者： Yanhua Li Youhui Zhang Jianfeng Yang Wayne Luk Guangwen Yang Weimin Zheng Department of Computer Science and Technology Tsinghua University Beijing China Department of Computing Imperial College London UK

Architecture customization is believed as one of the most promising methods to meet ever-increasing computing needs and power density limitations. this paper presents an approach to enhance a preliminary customizable core with some common architecture features, to adapt to the specific applications while keeping the programming flexibility. those features include several effective software/hardware co-optimizing strategies, such as loop tiling, pre-fetching, cache customization, customized Single Instruction Multiple Data (SIMD) and Direct Memory Access (DMA), as well as the necessary ISA extensions. Currently we select stencil computation as the research target. Detailed tests of power-efficiency to evaluate the effect of all these optimizations comprehensively shows impressive performance speedup and power efficiency, even compared to X86, GPU and FPGA platforms. All these proposed customizations here could be applied to other computing applications.

关键词： Optimization Hardware Energy consumption Computer architecture Graphics processing units field programmable gate arrays

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Radix-4 and radix-8 booth encoded interleaved modular multipliers over general Fp

Radix-4 and radix-8 booth encoded interleaved modular multip...

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international conference on field programmable logic and applications

作者： Khalid Javeed Xiaojun Wang Dublin City University Dublin IE School of Electronics EngineeringDublin City University Dublin Ireland

this paper presents radix-4 and radix-8 Booth encoded modular multipliers over general F p based on inter-leaved multiplication algorithm. An existing bit serial interleaved multiplication algorithm is modified using radix-4, radix-8 and Booth recoding techniques. the modified radix-4 and radix-8 versions of interleaved multiplication result in 50% and 75% reduction in required number of clock cycles for one modular multiplication over the corresponding bit serial interleaved multipliers, while maintaining a competitive critical path delay. the proposed architectures are implemented in Verilog HDL and synthesized by targeting virtex-6 FPGA platform. Due to an efficient utilization of optimized addition chains available in FPGAs and exploiting the parallelism among operations, the proposed radix-4 and radix-8 multipliers compute one 256 × 256 bit modular multiplication in 1.49μs and 0.93μs respectively, which are 35% and 94% improvement over the corresponding bit serial version. Further, this work also presents a thorough comparison on basis of area, throughput, and area × time per bit value. Which shows that these designs are efficiently optimized for area × time per bit value with a high throughput rate. thus, these designs are suitable to construct most of the elliptic curve and pairing based cryptographic processors.

关键词： Clocks Computer architecture field programmable gate arrays Registers Algorithm design and analysis throughput Hardware

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Using buffer-to-BRAM mapping approaches to trade-off throughput vs. memory use

Using buffer-to-BRAM mapping approaches to trade-off through...

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international conference on field programmable logic and applications

作者： Jasmina Vasiljevic Paul Chow Department of Electrical and Computer Engineering University of Toronto Toronto Ontario Canada

One of the challenges in designing high-performance FPGA applications is fine-tuning the use of limited on-chip memory storage among many buffers in an application. To achieve desired performance and meet the on-chip memory budget requirements, the designer faces the burden of manually assigning application buffers to physical on-chip memories. Mismatches between dimensions (bit-width and depth) of buffers and physical on-chip memories lead to underutilized memories. Memory utilization can be increased via buffer packing - grouping buffers together and implementing them as a single memory, at the expense of data throughput. However, identifying buffer groups that result in the least amount of physical memory is a combinatorial problem with a large search space. this process is time consuming and non-trivial, particularly with a large number of buffers of various depths and bit widths. Previous work [1] introduced a tool that provides high-level pragmas allowing the user to specify global memory requirements, such as an application's on-chip memory budget and data throughput. this paper extends the previous work by introducing two low-level pragmas that specify information about memory access patterns, resulting in an improved on-chip memory utilization up to 22%. Further, we develop a simulated annealing based buffer packing algorithm, which reduces the tool's run-time from over 30 mins down to 15 sec, with an improvement in performance in the generated memory solution. Finally, we demonstrate the effectiveness of our tool with four stream application benchmarks.

关键词： Buffer storage throughput field programmable gate arrays System-on-chip Memory management Benchmark testing Hardware design languages

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Hardware system synthesis from Domain-Specific Languages

Hardware system synthesis from Domain-Specific Languages

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international conference on field programmable logic and applications

作者： Nithin George HyoukJoong Lee David Novo Tiark Rompf Kevin J. Brown Arvind K. Sujeeth Martin Odersky Kunle Olukotun Paolo Ienne Ecole Poly technique Fédérale de Lausanne (EPFL) School of Computer and Communication Sciences

field programmable Gate Arrays (FPGAs) are very versatile devices, but their complicated programming model has stymied their widespread usage. While modern High-Level Synthesis (HLS) tools provide better programming models, the interface they offer is still too low-level. In order to produce good quality hardware designs with these tools, the users are forced to manually perform optimizations that demand detailed knowledge of both the application and the implementation platform. Additionally, many HLS tools only generate isolated hardware modules that the user still needs to integrate into a system design before generating the FPGA bitstream. these problems make HLS tools difficult to use for application developers who have little hardware design knowledge. To address these problems, we propose an automated methodology to generate FPGA bitstreams from high-level programs written in Domain-Specific Languages (DSLs). We leverage the domain-knowledge conveyed by the DSL and its domain-specific semantics to extract application parallelism, perform optimizations and also identify a suitable system-architecture for the implementation, thereby, relieving the user from most of the hardware-level details. We demonstrate the high productivity and high design quality this approach offers by automatically generating hardware systems from applications written in OptiML, a machine-learning DSL. To evaluate our methodology, we use four OptiML applications and show that we can easily generate different solutions which achieve different trade-offs between performance and area. More importantly, the results reveal that our generated hardware achieves much better performance compared to the one obtained from using the HLS tool without platform-specific optimizations.

关键词： Hardware Kernel Optimization DSL field programmable gate arrays Data structures Parallel processing

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High level programming framework for FPGAs in the data center

High level programming framework for FPGAs in the data cente...

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international conference on field programmable logic and applications

作者： Oren Segal Martin Margala Sai Rahul Chalamalasetti Mitch Wright Department of Electrical and Computer Engineering University of Massachusetts Lowell Lowell MA Silicon Design Lab HP Servers Houston TX

Heterogeneous computing offers a promising solution for energy efficient computing in the data center. FPGA based heterogeneous computing is an especially promising direction since it allows for the creation of custom hardware solutions for data centric parallel applications. One of the main issues delaying wide spread adoption of FPGAs as main stream high performance computing devices is the difficulty in programming them. OpenCL was meant to address the difficulties and the non-uniformity related to programming heterogeneous devices, unfortunately because of its complexity it sets the bar high for many software programmers, preventing them from directly benefiting from the computing power and energy efficiency that OpenCL and heterogeneous computing have to offer. this work presents an effort to bridge the gap by extending an existing Java programming framework (APARAPI), based on OpenCL, so that it can be used to program FPGAs at a high level of abstraction and increased ease of programmability. We run several real world algorithms to assess the performance of the APARAPI framework on both a low end and a high end system. On the low end and high and systems respectively we find up to 78-80 percent power reduction and 4.8X-5.3X speed increase running NBody simulation, as well as up to 65-80 percent power reduction and 6.2X-7X speed increase for a K-Means MapReduce algorithm running on top of the Hadoop framework and APARAPI.

关键词： field programmable gate arrays Algorithm design and analysis Programming Java Kernel Computer architecture

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A highly-efficient and green data flow engine for solving euler atmospheric equations

A highly-efficient and green data flow engine for solving eu...

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international conference on field programmable logic and applications

作者： Lin Gan Haohuan Fu Chao Yang Wayne Luk Wei Xue Oskar Mencer Xiaomeng Huang Guangwen Yang Department-of Computer-Science and Technology Tsinghua University Tsinghua National Laboratory for Information Science and Technology (TNList) Ministrv of Education Key Laboratory for Earth System Modeling Tsinghua University Institute of Software Chinese Academy of Sciences Department of Computing Imperial College London Mexeler Technologies

Atmospheric modeling is an essential issue in the study of climate change. However, due to the complicated algorithmic and communication models, scientists and researchers are facing tough challenges in finding efficient solutions to solve the atmospheric equations. In this paper, we accelerate a solver for the three-dimensional Euler atmospheric equations through reconfigurable data flow engines. We first propose a hybrid design that achieves efficient resource allocation and data reuse. Furthermore, through algorithmic offsetting, fast memory table, and customizable-precision arithmetic, we map a complex Euler kernel into a single FPGA chip, which can perform 956 floating point operations per cycle. In a 1U-chassis, our CPU-DFE unit with 8 FPGA chips is 18.5 times faster and 8.3 times more power efficient than a multicore system based on two 12-core Intel E5-2697 (Ivy Bridge) CPUs, and is 6.2 times faster and 5.2 times more power efficient than a hybrid unit equipped with two 12-core Intel E5-2697 (Ivy Bridge) CPUs and three Intel Xeon Phi 5120d (MIC) cards.

关键词： Mathematical model Atmospheric modeling Equations field programmable gate arrays Computational modeling Kernel three-dimensional displays

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Ultrasmall: the smallest MIPS soft processor

Ultrasmall: The smallest MIPS soft processor

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international conference on field programmable logic and applications

作者： Hiroshi Nakatsuka Yuichiro Tanaka thiem Van Chu Shinya Takamaeda-Yamazaki Kenji Kise Tokyo Kogyo Daigaku Meguro-ku Tokyo JP Tokyo Institute of Technology Tokyo Japan Tokyo Institute of Technology Meguro-ku Tokyo JP Nara Sentan Kagaku Gijutsu Daigakuin Daigaku Ikoma Nara JP

Soft processors have been commonly used in FPGAbased designs to perform various useful functions. Some of these functions are not performance-critical and required to be implemented using very few FPGA resources. For such cases, it is desired to reduce circuit area of the soft processor as much as possible. this paper proposes Ultrasmall, a small soft processor for FPGAs. Ultrasmall supports a subset of the MIPS-I ISA and is designed for microcontrollers in FPGA-based SoCs. Ultrasmall employs an area efficient architecture to minimize the use of FPGA resources. While supporting the 32-bit ISA, Ultrasmall adopts the 2-bit wide serial ALU architecture. this approach significantly reduces the amount of FPGA resource usage. In addition to the device-independent optimizations for any FPGAs, we apply primitives-based optimizations for the Xilinx Spartan-3E FPGA series with 4-input LUTs, thereby further reducing the total number of occupied slices. the evaluation result shows that, on the Xilinx Spartan-3E XC3S500E FPGA, Ultrasmall occupies only 137 slices which is 84% of the number of occupied slices of Supersmall, a very small soft processor with the same design concept as Ultrasmall. On the other hand, in term of performance, Ultrasmall is 2.9× faster than Supersmall.

关键词： field programmable gate arrays Shift registers Hardware Multiplexing Table lookup Optimization

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Cost-efficient FPGA layered LDPC decoder with serial AP-LLR processing

Cost-efficient FPGA layered LDPC decoder with serial AP-LLR ...

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international conference on field programmable logic and applications

作者： Oana Boncalo Alexandru Amaricai Andrei Hera Valentin Savin Computer Engineering Department University Politehnica Timisoara Timisoara Romania CEA-LETI MINATEC Campus Grenoble France val entin

this paper proposes an FPGA based layered architecture for quasi-cyclic (QC) irregular LDPC decoder. Our approach is based on merging variable and check node processing into one single variable-check node (VCN) unit. Layer message computation is done using a parallel scheme of a number of VCNs equal to the expansion factor of the QC matrix. the proposed architecture is characterized by the serial processing of the a posteriori LLRs by an FPGA specific high frequency VCN unit implementation using ROM memories. In our approach data conversions as well as additions and comparators are replaced by look-up-tables implemented using distributed RAM. In addition to this, other techniques such as: efficient packaging of LLRs messages and check-node message compression as well as the configurable port width of the FPGA's BRAM are used to reduce BRAM block utilization. throughput increase is achieved by utilizing techniques such as pipelining, parallel processing of multiple VCNs, as well as relatively high working frequency. Implementation results for the WiMAX (1152, 2304) QC irregular LDPC code indicate that the proposed architecture has up to 3x less slices resource utilization and up to 1 order of magnitude less BRAM blocks with respect to other approaches, while maintaining a throughput of several hundreds of Mbps (800 Mbps coded bits). We achieved this without sacrificing flexibility; therefore we can easily adapt our design to accommodate different code rates.

关键词： Parity check codes Decoding field programmable gate arrays throughput Read only memory Computer architecture Quantization (signal)

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Improve defect tolerance in a cluster of a SRAM-based Mesh of Cluster FPGA using hardware redundancy

Improve defect tolerance in a cluster of a SRAM-based Mesh o...

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international conference on field programmable logic and applications

作者： Adrien Blanchardon Roselyne Chotin-Avot Habib Mehrez Emna Amouri CNRS Paris France Sorbonne Universités UPMC Univ Paris 06 Paris France Institut TELECOM TELECOM ParisTech. Paris France

the technological evolution involves a higher number of physical defects in circuits after manufacturing. One of the future challenge is to find a way to use a maximum of defected manufactured circuits. In this paper, multiple techniques are proposed to avoid defects in the cluster local interconnect of a SRAM-based Mesh of Clusters FPGA. Using defect tolerance, area and timing metrics, two previous hardware redundancy strategies are evaluated on the Mesh of Clusters architecture : Fine Grain Redundancy (FGR) and Improved Fine Grain Redundancy (IFGR). We show that using these techniques on a cluster of a Mesh of Clusters architecture permits to tolerate 8 times more defects than on an industrial Mesh FPGA with a low area overhead (-6% for FGR and 22% for IFGR) and a low increase of Critical Path Delay (CPD)(6% for FGR and 2% for IFGR). We also proposed three new redundancy strategies using spare resources : Distributed Feedbacks (DF) for crossbar down, Adapted Fine Grain Redundancy (AFGR) to avoid defective multiplexers and Upward Redundant Multiplexer (URM) for the crossbar up. Compared to the Mesh of Clusters architecture without defect tolerance techniques, the best trade off between defect tolerance (36.4%), area overhead (11.56%) and CPD (+7.46%) is obtained using AFGR. Using the other methods permits to considerably limit the area overhead (10.4% with URM) with a lesser number of defective elements bypassed (18% max).

关键词： field programmable gate arrays Multiplexing Redundancy Delays Hardware Integrated circuit interconnections

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A scalable, high-performance customized priority queue

A scalable, high-performance customized priority queue

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international conference on field programmable logic and applications

作者： Muhuan Huang Kevin Lim Jason Cong Computer Science Department University of California Los Angeles Hewlett Packard Labs

Priority queues are abstract data structures where each element is associated with a priority, and the highest priority element is always retrieved first from the queue. the data structure is widely used within databases, including the last stage of a merge-sort, forecasting read-ahead I/O to stream data for the merge-sort, and replacement selection sort. Typical software implementations use a balanced binary tree-based structure, providing O(log N) time for both enqueue and dequeue operations. To improve the performance, we propose several scalable and high-speed FPGA-based implementations of a priority queue. Our insight is that the above listed applications primarily use priority queues through “replace” operations, which remove the highest priority element and place a new element into the queue. thus, our designs are customized for this operation, allowing for a simple and scalable architecture. We implement three priority queue designs, including use of a register-based array, register-based tree, and BRAM-based tree, which have different benefits and trade-offs of throughput, frequency, and maximum size. More importantly, all designs achieve O(1) time between replace operations. To incorporate the best aspects of our designs, we propose a Hybrid Priority Queue (H-PQ), which combines a register-based array with multiple BRAM-based trees. this design provides, on average, very fast access times to the top items in the queue (through the register-based array), while scaling to large priority queue sizes (through the BRAM-based trees). In our evaluations, we find that H-PQ achieves 4.3x speedup and 21.5x energy efficiency, compared with the Xeon CPU implementations.

关键词： throughput field programmable gate arrays Arrays Registers Clocks Software Database systems

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