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检索条件"任意字段=25th International Conference on Field Programmable Logic and Applications"

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A scalable and compact systolic architecture for linear solvers

A scalable and compact systolic architecture for linear solv...

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international conference on Application Specific Systems (ASAP), Architectures and Processors

作者： Kevin S. H. Ong Suhaib A. Fahmy Keck-Voon Ling Nanyang Technological University Singapore Singapore SG

We present a scalable design for accelerating the problem of solving a dense linear system of equations using LU Decomposition. A novel systolic array architecture that can be used as a building block in scientific applications is described and prototyped on a Xilinx Virtex 6 FPGA. this solver has a throughput of around 3.2 million linear systems per second for matrices of size N=4 and around 80 thousand linear systems per second for matrices of size N=16. In comparison with similar work, our design offers up to a 12-fold improvement in speed whilst requiring up to 50% less hardware resources. As a result, a linear system of size N=64 can be implemented on a single FPGA, whereas previous work was limited to a size of N=12 and resorted to complex multi-FPGA architectures to scale. Finally, the scalable design can be adapted to different sized problems with minimum effort.

关键词： field programmable gate arrays Arrays Hardware Linear systems Digital signal processing Educational institutions

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Pipelined reconfigurable accelerator for ordinal pattern encoding

Pipelined reconfigurable accelerator for ordinal pattern enc...

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international conference on Application Specific Systems (ASAP), Architectures and Processors

作者： Ce Guo Wayne Luk Stephen Weston Department of Computing Imperial College London London United Kingdom Maxeler Technologies London United Kingdom

Ordinal analysis is a statistical method for analysing the complexity of time series. this method has been used in characterising dynamic changes in time series, with various applications such as financial risk modelling and biomedical signal processing. Ordinal pattern encoding is a fundamental calculation in ordinal analysis. It is computationally demanding particularly for high query orders and large time series data. this paper presents the first reconfigurable accelerator for this encoding calculation, with four main contributions. First, we propose a two-level hardware-oriented ordinal pattern encoding scheme to avoid sequence sorting operations in the accelerator, enabling theoretically best code compactness. Second, we develop a hardware mapping method by promoting data reuse, by parallelising arithmetic operations, and by pipelining the data path. third, we conduct an experimental implementation of the proposed system, showing promising accelerated performance compared to software solutions. Finally, we apply the proposed accelerator to the computation of permutation entropy, demonstrating the significant potential for acceleration that would benefit such computation.

关键词： Encoding Time series analysis Hardware Acceleration Sorting field programmable gate arrays Computer architecture

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Low latency FPGA acceleration of market data feed arbitration

Low latency FPGA acceleration of market data feed arbitratio...

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international conference on Application Specific Systems (ASAP), Architectures and Processors

作者： Stewart Denholm Hiroaki Inoue Takashi Takenaka Tobias Becker Wayne Luk Department of Computing Imperial College London London UK NEC Corporation Kawasaki Japan

A critical source of information in automated trading is provided by market data feeds from financial exchanges. Two identical feeds, known as the A and B feeds, are used in reducing message loss. this paper presents a reconfigurable acceleration approach to A/B arbitration, operating at the network level, and supporting any messaging protocol. the key challenges are: providing efficient, low latency operations; supporting any market data protocol; and meeting the requirements of downstream applications. To facilitate a range of downstream applications, one windowing mode prioritising low latency, and three dynamically configurable windowing methods prioritising high reliability are provided. We implement a new low latency, high throughput architecture and compare the performance of the NASDAQ TotalView-ITCH, OPRA and ARCA market data feed protocols using a Xilinx Virtex-6 FPGA. the most resource intensive protocol, TotalView-ITCH, is also implemented in a Xilinx Virtex-5 FPGA within a network interface card. We offer latencies 10 times lower than an FPGA-based commercial design and 4.1 times lower than the hardware-accelerated IBM PowerEN processor, with throughputs more than double the required 10Gbps line rate.

关键词： Feeds Protocols field programmable gate arrays Reliability Acceleration throughput Delays

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Pipelined modular multiplier supporting multiple standard prime fields

Pipelined modular multiplier supporting multiple standard pr...

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international conference on Application Specific Systems (ASAP), Architectures and Processors

作者： H. Alrimeih D. Rakhmatov Cyber Security Centre Saudi Arabia ECE Department University of Victoria Victoria Canada

Computationally-intensive cryptographic applications are critically dependent on the efficiency of modular multiplications. It is desirable for a modular multiplier to offer not only high performance, but also a certain degree of flexibility, supporting multiplications over finite fields of varying size. We propose a fast and flexible modular multiplier over five prime fields GF(p), standardized by NIST for use in elliptic curve cryptography, where the five special primes p are of size 192, 224, 256, 384, and 521 bits. A prime-specific datapath configuration of our multiplier is established automatically, based on an external control word that identifies a NIST prime in use. the pipeline latency of our multiplier (implemented on a Virtex-6 FPGA and running at 100 MHz) is 80 ns for 192-bit, 224-bit, and 256-bit NIST primes, and 200 ns for 384-bit and 521-bit NIST primes. the main limitation of this work is that our multiplier currently supports only the NIST prime fields. We believe that such a limitation is justifiable, as the NIST prime fields are widely used in practice and enable performance improvements through specialized hardware optimizations.

关键词： NIST Clocks Zirconium field programmable gate arrays Pipelines Hardware throughput

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On the characterization of OpenCL dwarfs on fixed and reconfigurable platforms

On the characterization of OpenCL dwarfs on fixed and reconf...

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international conference on Application Specific Systems (ASAP), Architectures and Processors

作者： Konstantinos Krommydas Wu-chun Feng Muhsen Owaida Christos D. Antonopoulos Nikolaos Bellas Department of Computer Science Virginia Tech Department of Electrical and Computer Engineering University of Thessaly

the proliferation of heterogeneous computing platforms presents the parallel computing community with new challenges. One such challenge entails evaluating the efficacy of such parallel architectures and identifying the architectural innovations that ultimately benefit applications. To address this challenge, we need benchmarks that capture the execution patterns (i.e., dwarfs or motifs) of applications, both present and future, in order to guide future hardware design. Furthermore, we desire a common programming model for the benchmarks that facilitates code portability across a wide variety of different processors (e.g., CPU, APU, GPU, FPGA, DSP) and computing environments (e.g., embedded, mobile, desktop, server). As such, we present the latest release of OpenDwarfs, a benchmark suite that currently realizes the Berkeley dwarfs in OpenCL, a vendor-agnostic and open-standard computing language for parallel computing. Using OpenDwarfs, we characterize a diverse set of fixed and reconfigurable parallel platforms: multicore CPUs, discrete and integrated GPUs, Intel Xeon Phi coprocessor, as well as a FPGA. We describe the computation and communication patterns exposed by a representative set of dwarfs, obtain relevant profiling data and execution information, and draw conclusions that highlight the complex interplay between dwarfs' patterns and the underlying hardware architecture of modern parallel platforms.

关键词： Benchmark testing field programmable gate arrays Graphics processing units Hardware Computer architecture Kernel High definition video

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DRECON: DPA Resistant Encryption by Construction

DRECON: DPA Resistant Encryption by Construction

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7th international conference on Cryptology in Africa (AFRICACRYPT)

作者： Hajra, Suvadeep Rebeiro, Chester Bhasin, Shivam Bajaj, Gaurav Sharma, Sahil Guilley, Sylvain Mukhopadhyay, Debdeep Indian Inst Technol Kharagpur Dept Comp Sci & Engn Kharagpur W Bengal India TELECOM ParisTech Inst MINES TELECOM Dept COMELEC F-75634 Paris 13 France Secure IC SAS F-35700 Rennes France

ISBN: (纸本)9783319067339;9783319067346

Side-channel attacks are considered as one of the biggest threats against modern crypto-systems. this motivates the design of ciphers which are naturally resistant against side-channel attacks. the present paper proposes a scheme called DRECON to construct a block cipher with innate protection against differential power attacks (DPA). the scheme is motivated by tweakable block ciphers and is shown to be secure against first-order DPA using information theoretic metrics. DRECON is shown to be less expensive than masking and re-keying countermeasures from the implementation perspective and can be efficiently realized in both hardware and software platforms. On FPGAs especially, DRECON can optimally utilize the abundant block RAMs available and therefore have minimal overheads. We estimate the cost overhead of DRECON in micro-controllers and FPGAs, two common targets for cryptographic applications. Finally we demonstrate practical side-channel resistance of a DRECON implementation on a Xilinx Virtex-5 FPGA (SASEBO GII board).

关键词： field programmable gate arrays (FPGA)

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Automatic generation of parallelized FFT logic for implementation in FPGA chips

Automatic generation of parallelized FFT logic for implement...

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Annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS)

作者： Tayler Sokalski Naraig Manjikian Nakina Systems Ottawa Ontario Canada Department of Electrical and Computer Engineering Queen's University Kingston Ontario Canada

this paper considers the automatic generation of parallelized fast-Fourier-transform (FFT) logic for field-programmable gate-array (FPGA) chips. A custom software tool has been created to generate VHDL logic descriptions for parallelized radix-4 FFT architectures using decimation-in-frequency (DIF). these architectures accept N simultaneously-provided fixed-point complex-valued input samples every cycle for applications that demand high throughput. Two approaches are described for generating the product terms in complex multiplications involving twiddle constants: standard single-cycle multiplication, and multi-cycle shift-and-add multiplication. Synthesis results are reported for parallelized FFT implementations of different sizes targeting low-cost Cyclone III chips and high-end Stratix III and IV chips from Altera. the shift-and-add approach for constant multiplication is shown to consume more logic resources, but provide a higher maximum clock frequency.

关键词： field programmable gate arrays Hardware Standards Clocks Software tools Computer architecture Cyclones

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FDSOI applications and opportunity in China

FDSOI applications and opportunity in China

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international conference on Solid-State and Integrated Circuit Technology

作者： Zhongli Liu Kai Zhao Institute of Microelectronics Chinese Academy of Sciences Beijing China Institute of Semiconductors Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781479932849

Most of the electronic products are faced with a problem of energy conservation. the mobile electronic products and space applications in particular require ICs with low voltage and low power. the development for bulk Si even PDSOI CMOS in these aspects encounters a great challenge. FDSOI namely full depletion silicon on insulator is a very good alternative. When devices further scale down to the nanometer level, the advantage of energy saving of FDSOI is more prominent. this paper introduces advantages and applications of FDSOI as well as its development opportunity in China.

关键词： Random access memory Abstracts Junctions Reliability Ions logic gates field programmable gate arrays

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Labview FPGA FOC implementation for synchronous Permanent Magnet Motor Speed Control

Labview FPGA FOC implementation for synchronous Permanent Ma...

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IEEE/IAS international conference on Industry applications (INDUSCON)

作者： Matheus Alexandre Bevilaqua Ademir Nied José de Oliveira Whirlpool Corporation Motors Team State University of Santa Catarina - UDESC Joinville SC Brazil Grupo de Controle de Sistemas - GCS State University of Santa Catarina – UDESC Joinville SC Brazil

this paper describes an implementation of FOC (field Oriented Control) algorithm for speed control of a Permanent Magnet Synchronous Motor - PMSM. the motor considered is a Brushless-AC type - BLAC, with sinusoidal back-electromotive force - BEMF waveform, and the application intended for this motor is the direct drive - DD type of washing machines. the FOC algorithm is implemented using a National Instruments Labview FPGA System. this system is composed of a high level/high productivity tool for FPGA logic synthesis. the paper describes the design principles for FOC algorithm and then explains the implementation of the designed controllers in the Labview FPGA platform. Experimental results are provided to verify the FOC implementation.

关键词： Permanent magnet motors Induction motors field programmable gate arrays Load modeling Torque Rotors Synchronous motors

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Flexible reconfigurable architecture for DSP applications

Flexible reconfigurable architecture for DSP applications

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IEEE international SOC conference

作者： Abdulfattah M. Obeid Syed Manzoor Qasim Mohammed S. BenSaleh Zied Marrakchi Habib Mehrez Heni Ghariani Mohamed Abid King Abdulaziz City for Science And Technology Riyadh Al Riyadh Province SA Sorbonne Universite Campus Pierre et Marie Curie Paris ÃŽle-de-France FR Universite de Sfax Sfax TN

As the flexibility offered by fine-grained field programmable gate array (FPGA) comes at a significant cost of area, speed, and power, there is a trend to use coarse-grained architecture (CGA) for dataflow applications requiring high computational resources. Existing CGA solutions are characterized according to the general organization, the processing element architecture, the basic interconnect structure and their reconfiguration characteristics. Based on the study of several digital signal processing (DSP) applications and their implemented VLSI architectures, we propose a CGA with parameterizable and flexible blocks based on a generic matrix and interconnected by a configurable network. the proposed architecture provides a good tradeoff between flexibility and performance-density. A CAD tool is developed to automate the implementation of the design on the architecture. A synthesizable VHDL code generator is also developed in order to further explore and validate the proposed architecture. the unification of coarse-grained logic block and bus-based interconnection bridges the gap between application-specific integrated circuit (ASIC) and CGA, resulting in area reduction from 40× to 6×, respectively. Experimental results demonstrate the performance and efficiency of the proposed architecture to implement DSP designs.

关键词： Digital signal processing Multiplexing Routing Reconfigurable architectures Arrays Application specific integrated circuits field programmable gate arrays

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