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检索条件"任意字段=25th International Conference on Field Programmable Logic and Applications"

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Fuzzy logic for Omnidirectional Mobile Platform Control Based in FPGA and Bluetooth Communication

Fuzzy Logic for Omnidirectional Mobile Platform Control Base...

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Mexican international conference on Artificial Intelligence, MICAI

作者： Mario Pena-Cabrera J. Antonio-Gomez M. Roman Osorio Humberto Gomez Victor Lomas Ismael Lopez-Juarez Universidad Nacional Autónoma de México Mexico D.F. Mexico Universidad Nacional Autonoma de Mexico Coyoacan Distrito Federal MX Universidad Nacional Autónoma de México Mexico D.F. CINVESTAV Saltillo MEXICO

An Omni directional mobile platform control using the intelligence technique of Fuzzy logic is showed in the article, the control allows a practical and reliable driving control of 4 Omni directional wheels, implemented in FPGA allowing to have an independent and autonomous single chip system out of a central computer dependence in order to be used with different applications like service robots platforms. An additional feature is performed by using Bluetooth communication with a cellular phone based on a smartphone OS Android as the handset control device. Driving movement for the mobile platform is limited for 8 directions, a Fuzzy logic module controls the travelling of the platform with independent movement for each wheel, physical feedback is implemented by using electronic decoders.

关键词： Fuzzy logic field programmable gate arrays Mobile communication Wheels Pragmatics Mathematical model Fuzzy sets

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Analytical and comparative evaluation of advanced digital PWM control techniques

Analytical and comparative evaluation of advanced digital PW...

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IEEE Power India conference

作者： S. Banerjee D. Joshi M. Singh R. Sharma BVCOE New Delhi India DTU Delhi India NIT Kurukshetra India

the focus of this paper is the exploration of the technologies related to generation of digital signals which can be used for voltage control applications. three distinct methods have been described. the first one concerns with coding Pulse Width Modulation (PWM) and Sinusoidal PWM (SPWM) signals in Verilog and obtaining the output on a field programmable Gate Array (FPGA). the second technique relates to an FPGA with code dumped via Laboratory Virtual Instrumentation Engineering Workbench (LabView). LabView interfaced with ELVIS II kit to enable the generation of digital signals is the third implemented scheme. the features of these procedures are presented briefly along with their corresponding platforms. the benefits of using digital signals as compared to their analog counterparts have also been touched upon. the paper demonstrates Pulse Width Modulation (PWM) and multi-carrier Sine Pulse Width Modulation (SPWM) digital output. SPWM implemented by Verilog coding and dumped on FPGA, results in a huge reduction of cost and complexity as compared to other methods.

关键词： field programmable gate arrays Pulse width modulation Radiation detectors Hardware design languages logic gates Instruments Frequency modulation

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Program-based and model-based PLC design environment for multicore FPGA architectures

Program-based and model-based PLC design environment for mul...

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international conference on Informatics in Control, Automation and Robotics (ICINCO)

作者： Christoforos Economakos Michael Skarpetis George Economakos Technological Educational Institution of Sterea Ellada Department of Automation Engineering GR34400 Psahna Evia Greece National Technical University of Athens School of Electrical and Computer Engineering Microprocessors and Digital Systems Laboratory Heroon Polytechniou 9 GR15780 Zografou Greece

Digital design has been growing rapidly during the last years, offering advanced implementation solutions for a diversity of appliances and instruments, integrating different sensors and actuators. this has a great impact on embedded automation, where traditional programmable logic Controllers (PLCs) have been gradually replaced by high performance Embedded Controllers, Digital Signal Processor (DSP) chips and, more recently, power efficient field programmable Gate Arrays (FPGAs). Such new implementation platforms bring together efficient design methodologies, like model-based design and high-level or C level program-based design. In their turn, new design methodologies are accompanied by new design technologies like Intellectual Property (IP) based design and High-Level Synthesis (HLS). this paper presents a design environment that utilizes program-based and model-based design, for the development of PLC applications. Specifically, a tool flow is constructed that supports either the design of new control algorithms or the translation of existing algorithms into C. then, HLS and FPGA implementation tools are adopted, to implement the selected algorithms as multicore, embedded designs, offering performance improvements and hardware utilization efficiency. Overall, the proposed methodology and underlying tool flow support a novel high productivity prototyping platform for digital control applications, with very promising future extension capabilities.

关键词： field programmable gate arrays Algorithm design and analysis Hardware Digital signal processing Signal processing algorithms Microcontrollers Hardware design languages

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A 16-Bit Architecture of Advanced Encryption Standard for Embedded applications

A 16-Bit Architecture of Advanced Encryption Standard for Em...

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Frontiers of Information Technology (FIT)

作者： Imran Ali Gulistan Raja Ahmad Khalil Khan Department of Electrical Engineering University of Engineering and Technology Taxila Pakistan

Advanced Encryption Standard (AES) is the most widely used public cipher algorithm for crypto related applications in embedded systems. this paper presents an area efficient 16-bit AES architecture for key expansion, encryption and decryption. In the proposed design, a modular approach is adopted and it is capable of performing all transformations for 128, 192 and 256-bit cipher key lengths. the resources are reduced by minimizing the slice registers and BRAMs without compromising the throughput. the slice count is cut down by sharing the hardware logic resources. Instead of using separate memories for plain text, cipher text and intermediate results, only one BRAM is used. Also for cipher key and round keys, single BRAM is incorporated. the design is synthesized and implemented using Xilinx Virtex-5 FPGA. A comparison is made with existing architectures of different datapaths.

关键词： Encryption Ciphers throughput Hardware field programmable gate arrays Computer architecture Registers

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Specific MCU design of On board Unit in Electronic Toll Collection system 12th

Specific MCU design of On board Unit in Electronic Toll Coll...

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international conference on Solid-State and Integrated Circuit Technology

作者： Chunhui Yang Ligang Hou Junwei Yang Miao Liu Jinhui Wang Peiyuan Wan School of Electronic Information and Control Engineering Beijing University of Technology Beijing CHINA

ISBN: (纸本)9781479932849

A specific MCU design of On board Unit (OBU) in Electronic Toll Collection (ETC) system is proposed in this paper. According to the ETC applications,this MCU is designed to have the minimum application system. Results show that this MCU design scheme is feasible and fulfills the requirements of the central control chip used for OBU in ETC system. the MCU has about 113,000 gates, and its area is 642.74 μm × 494.20 μm under SMIC 65nm technology. the average power consumption is 98μW. Compared with the general MCU, the MCU has a larger advantage in ETC application.

关键词： Random access memory Read only memory field programmable gate arrays Educational institutions Abstracts logic gates System-on-chip

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A Feature-Driven Crossover Operator for Product Line Architecture Design Optimization

A Feature-Driven Crossover Operator for Product Line Archite...

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IEEE Annual international Computer Software and applications conference (COMPSAC)

作者： thelma Elita Colanzi Silvia Regina Vergilio Computer Science Departament of State University of Maringa (UEM) Maringa Brazil Computer Science Department Federal University of Parana (UFPR) Curitiba Brazil

ISBN: (纸本)9781479935765

the Product Line Architecture (PLA) design is a multi-objective optimization problem that can be properly solved in the Search Based Software Engineering (SBSE) field. However, the PLA design has specific characteristics. For example, the PLA is designed in terms of features and a highly modular PLA is necessary to enable the growth of a software product line. However, existing search based design approaches do not consider such needs. To overcome this limitation, this paper introduces a feature-driven crossover operator that aims at improving feature modularization. the proposed operator was applied in an empirical study using the multi-objective evolutionary algorithm named NSGAII. In comparison with another version of NSGAII that uses only mutation operators, the feature-driven crossover version found a greater diversity of solutions (potential PLA designs), with higher feature-based cohesion, and less feature scattering and tangling.

关键词： programmable logic arrays Measurement Sociology Statistics Genetics Couplings Unified modeling language

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FPGA implementation of high performance Fast Page Mode dynamic random access memory

FPGA implementation of high performance Fast Page Mode dynam...

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international conference on Software, Knowledge Information, Industrial Management and applications (SKIMA)

作者： Prajoy Podder Md. Mehedi Hasan Tanvir Zaman Khan Department of Electronics and Communication Engineering Khulna University of Engineering & Technology (KUET) Khulna Bangladesh

A digital system frequently requires memory for storage. To facilitate this requirement, FPGAs offer different types of memory, ranging from block RAM, a highly distributed RAM in the form of the multiple LUTs, right down to the storage of data in the flip-flops. However, unlike the conventional RAMs, dynamic random access memory (DRAM) is best suited for larger volumes of memory, because it permits complex yet advanced levels of integration, occupies less space in motherboard due to reduced feature size, and more importantly, it is inexpensive. Dynamic RAMs evolved from the earliest 1- kilobit (KB) generation to the modern 1-gigabit (GB) generation through the advances and developments in not only semiconductor process but also circuit design technology. this paper proposes resistor transistor logic (RTL) design of the firstgeneration and second-generation high performance (Fast Page Mode) dynamic random access memory. the simulation diagram was experimented using the Verilogger Test bench pro 6.5 software. the timing as well as device utilization summary has been presented in this paper and compared for both normal and fast page mode DRAM. For fast page mode DRAM, the combinational path delay was less compared to the first generation DRAM.

关键词： Random access memory Clocks Radiation detectors Memory management Process control Switches field programmable gate arrays

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Printing and encapsulation of electrical conductors on polylactic acid (PLA) for sensing applications

Printing and encapsulation of electrical conductors on polyl...

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IEEE international conference on Micro Electro Mechanical Systems

作者： Andrés Vásquez Quintero Nathalie Frolet Daniel Märki Alexis Marette Giorgio Mattana Danick Briand Nico F. de Rooij Ecole Polytechnique Fédérale de Lausanne (EPFL) Neuchâtel SWITZERLAND

this paper presents the printing of resistive and interdigitated (IDE) capacitive devices for temperature and humidity sensing applications, respectively, on biodegradable polylactic acid (PLA) substrates. Inkjet and gravure printing were evaluated to transfer silver-based nanoparticles inks. Flash photonic ink sintering methodologies were employed to maintain the PLA mechanical integrity due to its low glass transition temperature (58 °C). Between the two printing techniques investigated, gravure-printed devices on 200 μm-thick PLA sheets were shown to have better resolution and higher sensitivities to temperature and humidity (1100 ppmK -1 and 5.6 fF/%RH). Additionally, we demonstrated the inkjet printing of IDE onto thin (25 μm) dissolved-PLA spin-coated substrates, to enhance the mechanical flexibility and to reduce the response time to humidity (from 238 s to 70 s). Finally, a low temperature encapsulation is proposed by embedding the printed structures within PLA sheets.

关键词： programmable logic arrays Printing Humidity Substrates Ink Temperature sensors Films

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COMPACT IMPLEMENTATION OF CCM AND GCM MODES OF AES USING DSP BLOCKS

COMPACT IMPLEMENTATION OF CCM AND GCM MODES OF AES USING DSP...

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23rd international conference on field programmable logic and applications (FPL)

作者： de la Piedra, Antonio Touhafi, Abdellah Braeken, An Vrije Univ Brussel Dept Elect & Informat Brussels Belgium Eramushogesch Brussels IWT Brussels Belgium

In this manuscript, we have explored how the use of DSP blocks in the implementation of two authenticated-encryption modes of AES can optimize the PAR figures. Our results reflect that a 20.98 % reduction in slice uti... 详细信息

ISBN: (纸本)9781479900046

关键词： cryptography digital signal processing chips field programmable gate arrays

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A low-cost fully pipelined architecture for fingerprint matching

A low-cost fully pipelined architecture for fingerprint matc...

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international conference on Signal Processing Proceedings (ICSP)

作者： Jinwei Xu Jingfei Jiang Yong Dou Xiaolong Shen Science and Technology on Parallel and distributed Processing Laboratory National University of Defense Technology Changsha China

Fingerprint matching is a key procedure in fingerprint identification applications. the fingerprint-matching algorithm based on minutiae is one of the most typical algorithms that can achieve a reasonably correct recognition rate. Performance and cost are two critical factors when implementing minutia-based matching algorithms in most embedded applications. A low-cost, fully pipelined architecture for minutia-based fingerprint matching is proposed in this paper. A regular matching unit with a pipeline of 13 stages is designed as the core of the architecture, interfacing with a two-port RAM and a DDR3 controller. We implemented the whole architecture on a Xilinx FPGA board with the Virtex VII XC7VX485T chip. the matching unit can run with a frequency of 330 MHz on the chip, which leads the system to achieve a throughput of about 430000 fingerprints per second when processing typical datasets. the unit only occupies 568 slices, which is less than 1% of the available chip resources. the board only consumes 16 W of power when run. the architecture can gain about twice the throughput of the 2.93 GHz Intel Xeon5670 CPU at a low logic cost and power.

关键词： Fingerprint recognition throughput Random access memory Pipelines Computer architecture field programmable gate arrays Algorithm design and analysis

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