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检索条件"任意字段=25th International Conference on Field Programmable Logic and Applications"

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SHOULD FPGAS ABANDON thE PASS-GATE?

SHOULD FPGAS ABANDON THE PASS-GATE?

引用

23rd international conference on field programmable logic and applications (FPL)

作者： Chiasson, Charles Betz, Vaughn Univ Toronto Dept Elect & Comp Engn Toronto ON Canada

ISBN: (纸本)9781479900046

Pass-transistors have been the key building block for field-programmable gate array (FPGA) circuitry for many years due to the very small switch they enable. However, pass-transistor performance and reliability have been degrading with technology scaling. Transmission gates are an alternative to pass-transistors;while larger, they are more robust. We develop a new FPGA circuit optimization flow and use it to investigate the area, delay and power impact of building FPGAs out of transmission gates instead of pass-transistors in a 22nm process. Our results show that transmission gate FPGAs are 15% larger than pass-transistor FPGAs but are 10-25% faster depending on the allowable level of "gate boosting". Without gate boosting, transmission gate FPGAs are the better option with 14% lower area-delay product. If 200mV of gate boosting is possible however, pass-transistor FPGAs remain the slightly better choice with a 2% better area-delay product. We also show that transmission gates with a separate power supply for their gate terminal enable a low-voltage FPGA with 50% less power and good delay.

关键词： field programmable gate arrays integrated circuit reliability logic gates optimisation transistors

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DESIGN OF A MULTI GBPS SINGLE CARRIER DIGITAL BASEBAND FOR 60GHZ applications AND ITS FPGA IMPLEMENTATION

DESIGN OF A MULTI GBPS SINGLE CARRIER DIGITAL BASEBAND FOR 6...

引用

23rd international conference on field programmable logic and applications (FPL)

作者： Guntur, Surendra Jansen, Feike Hoogerbrugge, Jan Abkari, Lotfi Vos, Eric NXP Semicond Eindhoven Netherlands NXP Semicond Leuven Belgium

ISBN: (纸本)9781479900046

this paper describes the system architecture, design methodology and subsequent FPGA mapping of a millimeter wave digital baseband for wireless communication in the 60GHz spectral band. the baseband is designed to be compliant with the 802.11ad Single Carrier and Control PHY draft specifications and supports a data rate of 2.5Gbps at the physical layer. the demanding throughput and latency requirements are achieved with a parallel implementation. However, due to limited capacity of the FPGAs present in our prototype platform and complex partitioning requirements, only a scaled down version of the full single carrier baseband that operates at 1/10th the throughput of the specification could be mapped. A minimal real-time hardware MAC was also incorporated and coupled with a 60GHz RF beam-forming front-end to demonstrate file transfer between two independent FPGA prototyping systems. A system throughput of 59Mbps was achieved at the application layer using pi/2 QPSK modulation with a 13/16 LDPC code rate.

关键词： field programmable gate arrays parity check codes quadrature phase shift keying radiocommunication

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Multi-phase clocking based high precision Dielectric constant measurement for embedded applications

Multi-phase clocking based high precision Dielectric constan...

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4th Nirma University international conference on Engineering (NUiCONE)

作者： SandhyaRani, M. Soundararajan, K. NagabushanRaju, K. Intell Engn Coll Dept ECE Anantapur Andhra Pradesh India JNTUA Dept ECE Anantapur Andhra Pradesh India Sri Krishnadevaraya Univ Dept Instrumentat Anantapur 515003 Andhra Pradesh India

ISBN: (纸本)9781479907250

the precise estimation of dielectric constant is very essential requirement in several embedded applications. the cavity resonator and ring oscillator based techniques work well, but require costly setup for dielectric constant measurement. these techniques also become specific to a frequency range for precise estimation. the digital techniques for estimating the dielectric constant are investigated here. the field programmable Gate Array (FPGA) based hard wired digital logic with high precision computation is used for estimating the dielectric constant. the simulation and synthesis is carried out in Xilinx ISE environment and results are analyzed by varying the dielectric constant. the realized logic is synthesized to Spartan-6 FPGA and observed that only 10% of logic resources are occupied in Spartan-6 LX16 device, reporting maximum operable frequency of 300 MHz. As a result the proposed scheme can be used for dielectric constant measurement at any frequency up to 25 MHz.

关键词： dielectric constant digital phase estimation FPGA permittivity

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Recognizing User Preferences Based on Layered Activity Recognition and First-Order logic

Recognizing User Preferences Based on Layered Activity Recog...

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25th IEEE international conference on Tools with Artificial Intelligence (ICTAI)

作者： Glodek, Michael Geier, thomas Biundo, Susanne Schwenker, Friedhelm Palm, Guenther Univ Ulm Inst Neural Informat Proc Ulm Germany Univ Ulm Inst Artificial Intelligence Ulm Germany

ISBN: (纸本)9781479929719

Only few cognitive architectures have been proposed that cover the complete range from recognizers working on the direct sensor input, to logical inference mechanisms of classical artificial intelligence (AI). logical systems operate on abstract predicates, which are often related to an action-like state transition, especially when compared to the classes recognized by pattern recognition approaches. On the other hand, pattern recognition is often limited to static patterns, and temporal and multi-modal aspects of a class are often not regarded, e.g. by testing only on pre-segmented data. Recent trends in AI aim at developing applications and methods that are motivated by data-driven real world scenarios, while the field of pattern recognition attempts to push forward the boundary of pattern complexity. We propose a new generic architecture to close the gap between AI and pattern recognition approaches. In order to detect abstract complex patterns, we process sequential data in layers. On each layer, a set of elementary classes is recognized and the outcome of the classification is passed to the successive layer such that the time granularity increases. Layers can combine modalities, additional symbolic information or make use of reasoning algorithms. We evaluated our approach in an on-line scenario of activity recognition using three layers. the obtained results show that the combination of concepts from pattern recognition and high-level symbolic information leads to a prosperous and powerful symbiosis.

关键词： Layered architecture Conditioned hidden Markov model Markov logic network

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Accelerating 3D-FFT using Hard Embedded Blocks in FPGAs

Accelerating 3D-FFT using Hard Embedded Blocks in FPGAs

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26th international conference on VLSI Design Held Concurrently with 12th international conference on Embedded Systems Design

作者： Varma, B. Sharat Chandra Paul, Kolin Balakrishnan, M. Indian Inst Technol Delhi Dept Comp Sci & Engn New Delhi India

ISBN: (纸本)9780769548890

three dimensional Fast Fourier Transform (3D-FFT) is popularly used in many scientific applications in various domains like image processing, bioinformatics and molecular dynamics. Typically 3D-FFT computation takes significant part of the execution time of these applications. In order to speedup these applications, it becomes necessary to accelerate 3D-FFT computation. 3D-FFT can be accelerated using field programmable Gate Array (FPGA) based accelerators. But speedup always may not be possible as FPGAs run at slower clock frequency vis-avis processors and the resources available in an FPGA device might not be sufficient for the implementation of a sufficient number of copies of the processing elements to compensate for the loss of clock frequency. FPGAs with heterogeneous mix of coarse grained hard blocks along with programmable soft logic, can facilitate implementing a much larger number of processing elements and thus achieve much higher speedups. Modern FPGAs do consist of different heterogeneous hard embedded blocks (HEBs) like multipliers, DSP blocks and memory units. It is easy to predict that many more such hard blocks will be embedded into future FPGAs. the evaluation approach to identify and incorporate HEBs is complex as there are many parameters and constraints like area, granularity routing resources, etc. that need to be considered in an integrated manner to get an efficient implementation. In this paper we show acceleration of 3D-FFT using future fabrics incorporating HEBs. By using these fabrics we show speedups of upto 1900x for 2048 point FFT. We also present an evaluation methodology to design future FPGA fabrics incorporating accelerators as hard embedded blocks. this methodology will be useful for i selection of blocks to be embedded into the fabric and ii evaluating the performance gain that can be achieved by such an embedding.

关键词： clocks digital signal processing chips fast Fourier transforms field programmable gate arrays

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A New Intelligent programmable logic Controller based on Switched Networks

A New Intelligent Programmable Logic Controller based on Swi...

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9th international conference on Natural Computation (ICNC)

作者： Wang, Borui Wang, Guangfu Shandong Univ Sch Mech Elect & Informat Engn Weihai Shandong Peoples R China Electromech Inst Vocat & Technol Dept Training & Expt Panzhihua Peoples R China

ISBN: (纸本)9781467347143

this paper studies the design of a new intelligent PLC (programmable logic Controller) based on the switched network. It proposes a new solution for the Ethernet-based automation equipments and the related applications, which is used to control a variety of industrial processes in distributed locations. the points we discuss mainly involve Ethernet I/O architecture and the hardware design of communication module. For the field part, the scope of our control objects includes the remote I/Os and the interfaces with other equipments of this level, typically distributed I/Os & devices. For the devices of the architecture, we focus on discussing the hardware design of the communication module in our architecture. the design includes the system architecture with a new dual processer, reset signals and power supply supervisor, DDR (Double Data Rate) design, which has acted the kernel part in information exchange of IPLCBIE (Intelligent PLC based on Industrial Ethernet).

关键词： PLC industrial Ethernet switched network

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High Dimension CNF to DNF Conversion using Grid Computing

High Dimension CNF to DNF Conversion using Grid Computing

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15th international conference on Advanced Computing Technologies (ICACT)

作者： Momin, Bashirahamed F. Pardeshi, Mayuresh S. Walchand Coll Engn Dept Comp Sci & Engn Sangli MH India

ISBN: (纸本)9781467328166;9781467328180

CNF to DNF Conversion is considered as vast area of research by scientists for PLA's, circuit designs, FPGA's, artificial intelligence, etc. High dimension variable conversion has become a key demand in the current business standard. Various applications are in its requirement like gnome analysis, grid computing, bioinformatics, imaging system, rough sets requires higher variable processing algorithm. Problem statement is - Design and implementation of High dimension optimal conjunctive normal form to optimal (prime implicants) disjunctive normal form conversion which is an "NP hard problem conversion to an NP complete". thus CNF to DNF can only be considered to evaluate best performance for higher variable processing on high end systems. the best-known representations of Boolean functions f are those as disjunctions of terms (DNFs) and as conjunctions of clauses (CNFs). It is convenient to define the DNF size of f as the minimal number of terms in a DNF representing f and the CNF size as the minimal number of clauses in a CNF representing f.

关键词： CNF (conjunctive normal form) FPGA(field programmable gate arrays) DNF (disjunctive normal form) and PLA (programmable logic arrays)

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A Highly Integrable FPGA-Based Runtime-Configurable Multilayer Perceptron

A Highly Integrable FPGA-Based Runtime-Configurable Multilay...

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IEEE 27th international conference on Advanced Information Networking and applications (IEEE AINA)

作者： Skodzik, Jan Altmann, Vlado Wagner, Benjamin Danielis, Peter Timmermann, Dirk Univ Rostock Inst Appl Microelect & Comp Engn D-18051 Rostock Germany

ISBN: (纸本)9781467355506;9780769549538

In this paper, a highly integrable field programmable Gate Array-based hardware design of multilayer perceptron as a realization of an artificial neural network is presented. Such a hardware solution ensures a deterministic behavior required for any hard real-time compositions. the integration into existing systems is achieved by the application of UDP/IP. Additionally, the presented design is highly flexible due to a parameterizable multilayer perceptron approach. However, most reconfigurations usually require a hard coded reimplementation, resynthesis, and the download of a new bitfile to the target platform, which also requires an additional host PC. Contrary with the presented solution, it is possible to configure the multilayer perceptron's parameters during runtime via a software interface. this approach allows the multilayer perceptron to be adapted to nearly any application. the developed design combines the flexibility of a software solution to generate and comfortably reconfigure the multilayer perceptron as well as the high performance of a hardware solution. As proof of concept, a running prototype has been realized, which shows the design to be highly flexible and with good performance while the hardware resource consumption is kept minimal.

关键词： Artificial Neural Networks Multilayer perceptrons Reconfigurable logic Runtime

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A flexible interconnection structure for reconfigurable FPGA dataflow applications

A flexible interconnection structure for reconfigurable FPGA...

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2013 IEEE 37th Annual Computer Software and applications conference, COMPSAC 2013

作者： Durelli, Gianluca Nacci, Alessandro A. Cattaneo, Riccardo Pilato, Christian Sciuto, Donatella Santambrogio, Marco D. Politecnico di Milano Dipartimento di ElettronicaInformazione e Bioingegneria Milan Italy

ISBN: (纸本)9780769549798

Dataflow applications have proven to be well-suited for hardware implementation due to their intrinsic pipelined nature. Furthermore a wide range of algorithms, ranging from image analysis to map-reduce tasks, can be expressed using this paradigm. At the same time field programmable Gate Arrays (FPGA) start to be employed as hardware accelerators also in high-end systems coupled with General Purpose Processors (GPP). In this work we propose a programmable interconnection structure which permits to dynamically reconfigure the functionality of an FPGA implementing dataflow applications. A detailed analysis of the proposed solution shows that it is effectively able to increase the overall system flexibility helping in reducing the overall workload execution up to 25%, while at the same time reducing its variance. © 2013 IEEE.

关键词： field programmable gate arrays (FPGA)

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Digital synthesis architecture for modulation and demodulation

Digital synthesis architecture for modulation and demodulati...

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international conference on Microelectronics, ICM

作者： A. Benhaoues C. Tanougast H. Mayache S. Toumi A. Dandache LERICABadji-Mokhtar University Annaba Algeria ASEC Team University of Lorraine Metz France

Nowadays, the current challenge in the wireless digital systems is to design new digital, generic and “universal” architectures, take charge of functionalities previously managed by different circuits. Moreover, these ones must be sufficiently flexible to support multiple transmission standards and easily adaptable for future evolutions. In this work, we propose a digital architecture for modulation and demodulation using LFSR registers. the architecture was implemented on Xilinx Virtex series field programmable gate arrays (FPGA). the implementations demonstrate that our proposed architecture can deliver a high reduction of the FPGA logic requirements and consumption power when compared with the Velcro architecture.

关键词： field programmable gate arrays Demodulation logic gates Multiaccess communication Spread spectrum communication Convolutional codes Convolution

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