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检索条件"任意字段=25th International Conference on Field Programmable Logic and Applications"

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Realization of CNN Using Hybrid Multiplier With PYNQ-Z2

Realization of CNN Using Hybrid Multiplier With PYNQ-Z2

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international conference on Computing and Networking Technology (ICCNT)

作者： A. Umamaheswari S. Kripa V. Jeyalakshmi Department of ECE CEG Anna University Chennai India

ISBN: (数字)9798350370249

ISBN: (纸本)9798350370270

Smart technologies namely Machine Learning (ML) and Deep Learning (DL) are evolved day by day to develop smart products for various applications. Deep learning is one of the recent technology, which is widely applicable for all kind of applications. CNN (Convolutional Neural Network) is the basic structure to simulate the deep learning algorithms. So various structure of CNN is studied and the selected structure is used for classification of images. then the selected CNN structure is further analyzed for its performance in the FPGA (field programmable Gate Array) board. LeNet and EfficientNet uses MNIST and CIFAR-10 datasets to analyse the performance in both software and hardware. By comparing the performance of EfficientNet, it takes 124 ms in software and 0.172 ms in hardware to classify a single image. Whereas LeNet takes 19 ms and 0.16 ms in software and hardware respectively. CNN performance can be highly improved by exploring the hardware resources of the FPGA chip. An efficient multiplier is designed here for LeNet to reduce the utilization of hardware resources. By implementing it, the area utilized is reduced by $51.2 \%$ than by using conventional multiplier for CNN.

关键词： Deep learning Runtime Machine learning algorithms logic gates Hardware Software Real-time systems Classification algorithms Convolutional neural networks field programmable gate arrays

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A Reactive System-Specific Compilation Chain from Synchronous Dataflow Models to FPGA Netlist

A Reactive System-Specific Compilation Chain from Synchronou...

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IEEE international conference on Space Mission Challenges for Information Technology, SMC-IT

作者： Inès Winandy Arnaud Dion Pierre-Loïc Garoche Florent Manni Fédération ENAC ISAE-SUPAERO ONERA Université de Toulouse Toulouse France CNES - Centre national d'études spatiales Toulouse France

ISBN: (数字)9798350384512

ISBN: (纸本)9798350384529

Modern field programmable Gate Arrays (FPGAs) offer a solution to several issues related to real-time on-board systems, such as guaranteed execution time. they are currently considered as target platforms for space applications. How-ever, the complexity of producing circuits on these components poses a challenge to their widespread adoption. To address this issue, high-level synthesis tools provide another layer of abstraction above the logic circuit design process, for example compiling C code into Hardware Description Languages such as VHDL or Verilog. However, high-level synthesis results are poorly predictable and do not guarantee the efficient use of recent FPGA capabilities provided by new primitives like digital signal processor or random-access memory. In this paper we propose a compilation chain dedicated to reactive systems, ie. controllers, providing a more predictable synthesis process for critical embedded control applications. the implemented solution demonstrates timing performance equivalent to the traditional synthesis process with a more predictable result.

关键词： Solid modeling Analytical models VHDL Space missions Circuits Hardware Timing Numerical models Integrated circuit modeling field programmable gate arrays

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Design of High-Speed Multipliers using Counter based 4:2 Compressor with Pre-Processing

Design of High-Speed Multipliers using Counter based 4:2 Com...

引用

international conference on Information Technology and Electrical Engineering (ICITEE)

作者： Pavitra Y J Mahanta Talakal Department of Electronics and Communication Engineering PES University Bangalore India

ISBN: (数字)9798350375817

ISBN: (纸本)9798350375824

Adders and multipliers form the basic building blocks in most of the system designs. Multipliers are widely used in arithmetic and logic units, digital signal processing, audio processing, and image processing applications. Multipliers have complex structures and optimization of multiplier designs plays a vital role in improving the performance parameters like area, power, and delay. the proposed work aims to design compressor-based multipliers using counter logic for power and delay-efficient models. A novel 4:2 counter-based compressor with pre-processing is proposed to design multipliers to improve performance parameters like area power and delay. the proposed designs are synthesized on Cadence Genus with 90nm technology. Experiments carried out reveal that the proposed multipliers save a maximum of 21.71% of area, and 75.63% of power and improve speed by 24.28% over multipliers reported in the literature.

关键词： Electrical engineering Image coding Digital signal processing Delays logic Information technology System analysis and design Optimization field programmable gate arrays Arithmetic

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A Dataflow Overlay for Monte Carlo Multi-Asset Option Pricing on AMD Versal AI Engines

A Dataflow Overlay for Monte Carlo Multi-Asset Option Pricin...

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ISC High Performance 2025 Research Paper Proceedings (40th international conference)

作者： Mohamed Bouaziz Michael Samet Suhaib A. Fahmy KAUST Thuwal Saudi Arabia RWTH Aachen University Aachen Germany

ISBN: (数字)9783982633619

Monte Carlo simulations are widely used for financial applications, particularly in option pricing. Multi-asset option pricing has not been as widely investigated as single-asset problems and presents specific challenges. this paper presents an efficient way to design a dataflow overlay for multi-asset option pricing on AMD Versal AI Engines by leveraging their SIMD capabilities and the high-performance interconnect network linking them. the proposed dataflow overlay achieves a highly scalable parallelized implementation that can utilize nearly the totality of the available AI Engines on the AMD Versal VCK5000 accelerator. We also show that it achieves up to 25.7× speedup over a traditional FPGA programmable logic implementation using the Vitis Quantitive Finance Library, a specialized AMD library for quantitative finance on FPGAs, and up to 13.41× speedup over a highly parallelized CPU implementation over 128 threads. We show that although an Nvidia RTX A6000 GPU implementation has 0.73× the execution time of our design, our design achieves 1.82× the energy efficiency.

关键词： Pricing Engines Computational modeling Finance Artificial intelligence field programmable gate arrays Stochastic processes Mathematical models Computer architecture Accuracy

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FPGA Based Military Vehicle Classification from Drone-Based Video Using Deep Learning

FPGA Based Military Vehicle Classification from Drone-Based ...

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international conference on Frontiers of Signal Processing (ICFSP)

作者： S Vasavi D Sree Sowmya Ch Aishwarya Wendy Flores Fuentes Computer Science & Enigneering Velagapudi Ramakrishna Siddhartha Engineering College Vijayawada India Engineering Institute Autonomous University of Baja California Mexico

ISBN: (数字)9798350353235

ISBN: (纸本)9798350353242

Remotely controlled aerial vehicles such as drones are used for military applications such as surveillance, intelligence and target acquisition. Real-time object detection and classification is one of the most recurrent tasks for drones. the proposed system is used to classify the military vehicles from the drone-based videos. Object segmentation and classification of military vehicles (military tanks and APCs) is done using the Detectron2 and is based on Mask-RCNN benchmark. A custom dataset consisting of 300 images of Military Tanks and Armored Personnel Carriers (APCs) has been created and annotated for the purpose of the project. Furthermore, the Mask RCNN (Resnet50+FPN) model is trained with the custom dataset to classify the vehicles. the trained model is integrated in to field programmable Gate Arrays (FPGA), to carry out onboard classification in a real-time manner. Performance measures are used to evaluate the proposed model and overall accuracy is 93% with reduced false positive rate.

关键词： Array signal processing Surveillance Military vehicles logic gates Real-time systems Personnel field programmable gate arrays Videos Drones Remotely piloted aircraft

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Design and Development of Readout Electronics for thermopile Array Detector Using FPGA

Design and Development of Readout Electronics for Thermopile...

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international conference on Circuits, Communication, Control and Computing

作者： Rashmi Priyadarshini B K Rajendra Prasad P Mrinal Sarvagya Banothu Naresh Ravi Kumar M G School of Electronics and Communication Engineering REVA University Bangalore India Department of Electronics and Communication Engineering Ramaiah Institute of Technology Bangalore India Laboratory for Electro Optics Systems (LEOS) Indian Space Research Organization (ISRO) Bangalore India Department of Electronics and Communication Engineering & Technology Nagarjuna College of Engineering Bangalore India

ISBN: (数字)9798331528539

ISBN: (纸本)9798331528546

thermopile detector arrays, integral to infrared sensors, find widespread application in temperature measurement and thermal imaging. this paper introduces a novel approach by designing dedicated readout electronics for thermopile detectors, aiming at their characterization for space applications, specifically in a safe mode earth sensor. the proposed system employs a reprogrammable field programmable Gate Array (FPGA) for implementing the readout electronics, encompassing tasks such as extracting raw pixel data from the detector and configuring the sensor for different parameter settings. the safe mode earth sensor, crucial for spacecraft attitude determination, provides 2-axes attitude referencing Earth in the pitch and roll axes. Leveraging thermopile-based earth sensors, the system detects Earth edges in the IR band, facilitating the calculation of roll and pitch angles. the compact design makes it particularly suitable for deployment in Micro-Satellites and other satellites as a safe mode sensor. the readout electronics and data acquisition system play a pivotal role in evaluating, characterizing, and screening thermopile detectors, ensuring their suitability for deployment in safe mode earth sensor applications. this integrated approach not only enhances the efficiency of thermopile detectors but also opens avenues for their broader application in space-based sensing systems.

关键词： Earth Space vehicles Data acquisition Detectors Position measurement logic design logic Readout electronics field programmable gate arrays Sensor arrays

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16 Bit Memory and Power Efficient Truncated Booth Multiplier For High Speed applications/Operations

16 Bit Memory and Power Efficient Truncated Booth Multiplier...

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Mobile Computing and Sustainable Informatics (ICMCSI), international conference on

作者： Yashu Swami T. Senthil Vadivel Department of ECE MRIIRS Faridabad Haryana India Civil Engineering Department MRIIRS Faridabad Haryana India

ISBN: (数字)9798331522667

ISBN: (纸本)9798331522674

We now know that multipliers are a necessary component of all basic circuits. these days, multipliers are the cornerstone of any ALU system. High Radix Booth encoding reduces unfinished product during multiplication, but multipliers also introduce delay and power due to hard multiples. the approximate radix-256 Booth encoding is recommended in order to prevent hard multiples. By shifting and complimenting, a partial encoding method is used to construct partial product pairings. Precise encoding values are determined by adding up matching partial products. For performance testing, a 16x16 bit multiplier with the recommended radix-256 Booth encoding was built. Implementation of a 16-bit Truncated Booth Multiplier on the Nexys 4 DDR FPGA board. and contrast with additional multipliers.

关键词： Memory management Circuits Encoding Delays logic Informatics Mobile computing field programmable gate arrays Testing Arithmetic

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Scalable Convolutional Neural Network Inference on-the-Edge using Low-Density FPGAs

Scalable Convolutional Neural Network Inference on-the-Edge ...

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Advanced Research in Computing (ICARC), international conference on

作者： Udara Ranabahu S A Suraweera Arachchige W A Susantha Wijesinghe School of Engineering Liverpool John Moores University Liverpool United Kingdom Faculty of Applied Sciences Wayamba University of Sri Lanka Kuliyapitiya Sri Lanka

ISBN: (数字)9798331530983

ISBN: (纸本)9798331530990

Machine learning (ML) inference-based applications are often considered to be computationally expensive and power exhaustive, restricting useful deployment in low-power use cases. To take advantage of ML in power-constrained edge environments, it is critical to reduce the power consumption and increase the overall efficiency, while aiming for performance *** present a characteristics study of a low-powered implementation of ML inference focused on-the-edge, aiming for increased efficiency and predictive cost estimation. A scalable inference accelerator architecture for Convolutional Neural Networks (CNNs) consisting of simple functional blocks was developed at Register-transfer Level (RTL) using Verilog® Hardware Description Language (HDL), and was verified at RTL-level verification using RTL testbenches. the integrated system went through functional verification against a predefined golden model, while being optimized for precision and logic *** accelerator was then converted into a fully-parameterized Reconfigurable FPGA IP with additional purpose-built custom debugging glue logic; and validated on FPGA hardware. the system showed a minimum of 740 times acceleration factor during recorded performance evaluations.

关键词： Maximum likelihood estimation Costs Hardware Silicon Convolutional neural networks IP networks logic Resource management Hardware design languages field programmable gate arrays

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A Design of Fault-Tolerant System for Safety-Critical Systems

A Design of Fault-Tolerant System for Safety-Critical System...

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international conference on Autonomous Robots and Agents, ICARA

作者： Kai Yoshizawa Nobuyuki Yamasaki Graduate School of Science and Technology Keio University Yokohama Japan

ISBN: (数字)9798331509231

ISBN: (纸本)9798331509248

In safety-critical systems where failures or faults can lead to accidents, especially in special and harsh environments like those encountered in spacecraft, it is well known that multiple levels of errors can significantly increase the likelihood of system failure. For instance, system-level errors may occur due to cable breaks caused by severe vibrations, while gate-level errors can arise from radiation effects on System-on-Chip (SoC) semiconductors. Furthermore, in such specialized environments, human repair is often not feasible, necessitating that the system continue to operate even when a fault occurs in a part of it. therefore, this research discusses the design, implementation, and evaluation of a redundant system that combines multi-level redundancy mechanisms to tolerate multiple errors and maintain operation. the implementation was carried out on the Space I/O Core (SIOC), a System-on-Chip equipped with processors and I/O for distributed real-time systems. Additionally, bitstreams were created from the implemented logic, and the performance of the fault-tolerant system was evaluated using an actual FPGA.

关键词： Vibrations Space vehicles Redundancy Fault tolerant systems Termination of employment Switches logic gates System-on-chip field programmable gate arrays Robots

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Velocity control of Voice Coil Actuator using field programmable Gate Array

Velocity control of Voice Coil Actuator using Field Programm...

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international conference on Circuit, Power and Computing Technologies (ICCPCT)

作者： Manisha Joshi Pooja Ghadage Niyati Deshmukh Soniya Deshmukh Department of Electronics and Telecommunication Engineering V. E. S. Institute of Technology Mumbai India

ISBN: (数字)9798350372816

ISBN: (纸本)9798350372823

Voice Coil Actuators (VCA) find extensive applications across various domains such as loudspeakers, disk drives, and optical storage devices. Achieving precise velocity regulation poses a significant hurdle in effectively controlling VCA. this challenge arises due to the inherent dynamism and complex nonlinear attributes of VCA. this paper introduces an innovative FPGA-based velocity controller tailored specifically for VCA. the proposed controller integrates a dual-control approach comprising feedforward and feedback mechanisms to realize accurate velocity regulation. the feedforward component leverages a VCA model to anticipate its velocity based on the input current. Conversely, the feedback mechanism employs a Proportional-Integral-Derivative (PID) controller to rectify discrepancies between the anticipated and actual velocities. Experimental assessment of the proposed controller was conducted on a prototype VCA system. the outcomes demonstrated the controller's capability to achieve precise velocity regulation, even in the presence of external disturbances. Moreover, the controller exhibited adeptness in accurately tracking intricate velocity profiles. Compared to conventional analog controllers, the FPGA-based velocity controller offers several advantages. the versatility of the proposed controller renders it well-suited for an array of applications spanning robotics, automation, and industrial control.

关键词： Coils Vibrations Velocity control Position control field programmable analog arrays logic gates Regulation

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