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检索条件"任意字段=25th International Conference on Field Programmable Logic and Applications"

共 1846 条记录，以下是121-130 订阅

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Proceedings - 2018 international conference on field-programmable logic and applications, FPL 2018

Proceedings - 2018 International Conference on Field-Program...

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28th international conference on field-programmable logic and applications, FPL 2018

ISBN: (纸本)9781538685174

the proceedings contain 86 papers. the topics discussed include: a SAT-based timing driven place and route flow for critical soft ip;lightweight secure processor prototype on FPGA;an application-specific field-programmable tree ensemble architecture;facilitating easier access to FPGAs in the heterogeneous cloud ecosystems;a demo of FPGA aggressive voltage downscaling: power and reliability tradeoffs;digital pre-distortion implemented using FPGA;accelerated wire-speed packet capture at 200 Gbps;and vicilogic2.0 online learning and prototyping using pYNQ.

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FPGA Implementation of Polyphase CIC Based Multistage Filter for Digital Receivers 8

FPGA Implementation of Polyphase CIC Based Multistage Filter...

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8th international conference on Advanced Computing and Communication Systems, ICACCS 2022

作者： Latha, R. Venkatesan, C. Suhas, A.R. thamaraimanalan, T. Hkbk College of Engineering Department of Ece Bangalore India Sri Eshwar College of Engineering Department of Ece Tamilnadu Coimbatore India

ISBN: (纸本)9781665408165

the main focus of this work is to propose suitable architectures for the decimation filter networks of digital receivers that use the reduced logic and are capable of receiving multiple communication standard signals. It also involves the design, simulation, and implementation of multi-stage multi-rate filter architectures with reduced Very Large Scale Integrated (VLSI) cost functions. In the first multi-stage architecture namely, the Multi-Standard Decimation Filter (MSDF) structure is proposed to cater to the need of reception of multi-standard receiver signals. the MSDF architecture is designed for GSM and WiMAX wireless communication specifications and its first stages are designed using Cascaded Integrator Comb (CIC) filters. In the second architecture, a modified MSDF structure is implemented using polynomial CIC filters to meet the multi-standard requirements. the third architecture concentrates on design parameters of polyphase CIC-based decimation filter and its implementation concepts. Spartan FPGA-based implementation results that the proposed polynomial CIC-based MSDF architecture provides 32.11% of area reduction when related with the multistage MSDF. the proposed polyphase CIC-based MSDF architecture provides 28.57% of dynamic power-saving and a 15.5% increase in speed when compared to polynomial-based MSDFC architecture. thus, the proposed polyphase MSDF architecture provides low power and lesser delay solutions using a multistage decimation approach and it is best suited for multi-standard communication applications in digital receivers. © 2022 IEEE.

关键词： field programmable gate arrays (FPGA)

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FPGA-Based Digital FIR Filters With Small Coefficients and Large Data Input

FPGA-Based Digital FIR Filters With Small Coefficients and L...

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IEEE Annual Computing and Communication Workshop and conference (CCWC)

作者： Noureddine Chabini Rachid Beguenane Department of Electrical and Computer Engineering Royal Military College of Canada Kingston Ontario Canada

Digital Finite Impulse Response (FIR) filters are used in real-life applications. this paper proposes a divide and conquer approach to synthesis digital FIR filters with small coefficients and large data input on modern field programmable Gate Arrays (FPGAs). Xilinx Artix-7 is used in this work as an example of modern Xilinx 7-series FPGAs, which contains embedded DSP blocks to carry out 25×18 bits asymmetric multiplication and even addition operations. the synthesis is performed using the Xilinx Vivado 2020.2 synthesis tool. the proposed approach is compared to the traditional one which consists in coding the * operator in the VHDL language. Experimental results show that the proposed approach excels on the traditional one in terms of speed and area.

关键词： VHDL Finite impulse response filters conferences logic gates Encoding Arrays field programmable gate arrays

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FPGA-Based 3D EM/MPM Simulation Framework for Medical Image Segmentation applications

FPGA-Based 3D EM/MPM Simulation Framework for Medical Image ...

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international conference on Electronics, Materials Engineering and Nano-Technology (IEMENTech)

作者： Samit Karmakar Arindam Chakraborty Saptarshi Banerjee Ayantika Mondal Satavisha Dutta Sayak Nandi Electronics & Communication Engineering Dept. Institute of Engineering & Management University of Engineering & Management Kolkata India

ISBN: (数字)9798331520762

ISBN: (纸本)9798331520779

Medical image segmentation is a critical process in identifying disease-infected regions for diagnostic and treatment purposes. this paper introduces an FPGA-based framework for implementing the Expectation Maximization/Markov Random field (E M/MP M) algorithm in 3D medical image segmentation. FPGA platforms offer unparalleled advantages in terms of parallel processing, speed, and energy efficiency, making them a promising choice for real-time medical image analysis. this proposed framework enables rapid segmentation of 3D images, leveraging the FPGA's on-chip memory and custom logic for efficient pixel classification and data processing. the adaptive design also supports the integration of external RAM for larger datasets. Simulated using Verilog HDL and Quartus Prime, this work demonstrates accurate segmentation results through virtual testing, thus showcasing the system's robustness for medical applications.

关键词： Image segmentation three-dimensional displays Random access memory Medical services Parallel processing Real-time systems Energy efficiency Hardware design languages Medical diagnostic imaging field programmable gate arrays

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Design and Realization of Multi Channel programmable Power Supply SIP Based on FPGA

Design and Realization of Multi Channel Programmable Power S...

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international conference on (ICEPT) Electronic Packaging Technology

作者： Shaozhuang Jiang Guorong Han Yang Yang Yang Xue Qiang Jing R&D Department Shennan Circuits Co. Ltd. Shenzhen China

ISBN: (数字)9798350353808

ISBN: (纸本)9798350353815

Owing to its excellent parallel computing capabilities and distinctive on-site programmability, field-programmable Gate Array (FPGA) technology is deemed indispensable within specialized domains. Nonetheless, prevailing methodologies relying on discrete components to build power supply circuits for FPGA entail considerable drawbacks, including substantial footprint, elevated design expenditures, diminished stability, and pronounced electromagnetic interference, thereby circumscribing the breadth of FPGA utilization scenarios. this study endeavors to mitigate such constraints by devising a Power Management System-in-Package (SIP) featuring multiple independent and configurable power rails, tailored to the power exigencies of large-scale FPGA characterized by high core current demands and different power supply voltage levels for multiple BANKs. the proposed system integrates nine DC-DC units and one LDO unit to furnish autonomous power delivery to ten distinct power rails, each offering individually adjustable outputs. Programming control is realized through the utilization of compact logic devices for power enablement and millisecond-level timing management. the buried PCB technology is applied to encapsulate multiple active and passive devices into a single module measuring $22 \text{mm} \times 22 \text{mm} \times 7.4 \text{mm}$ . Experimental evaluation of the module's VOUT1 reveals an approximate conversion efficiency of 89.2% under typical output conditions of 1V10A. When configured solely with $2\times 22 \text{uF}$ ceramic capacitors and subjected to a substantial load of 20A, the observed output ripple remains $\leq 1.95\%$ . the module boasts a maximum total output power of 125W and exhibits robust operational stability within an environmental range spanning from -55°C to 85°C, with a notable maximum shock resistance acceleration exceeding $\geq 5000 \mathrm{g}$ . the embedded power module implemented in this study features multiple power rails,

关键词： Rails Resistance System-in-package Power supplies Multichip modules Power system stability Circuit stability

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High-Speed Chromatic Dispersion Compensation Filtering in FPGAs for Coherent Optical Communication 30

High-Speed Chromatic Dispersion Compensation Filtering in FP...

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30th international conference on field-programmable logic and applications (FPL)

作者： Bae, Cheolyong Gustafsson, Oscar Linkoping Univ Dept Elect Engn Linkoping Sweden

ISBN: (纸本)9781728199023

Chromatic dispersion is one of the error sources limiting the transmission capacity in coherent optical communication that can be mitigated with digital signal processing. In this paper, the current status and plans of implementation of chromatic dispersion compensation (CDC) filters on FPGAs are discussed. As these high-speed filters are most efficiently implemented in the frequency-domain, different approaches for high-speed FFT-based architectures are considered and preliminary results of fully parallel FFT implementation by utilizing FPGA hardware features are presented.

关键词： Chromatic dispersion compensation (CDC) fast Fourier transform (FFT) field-programmable gate arrays (FPGAs)

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Characterizing Latency Overheads in the Deployment of FPGA Accelerators 30

Characterizing Latency Overheads in the Deployment of FPGA A...

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30th international conference on field-programmable logic and applications (FPL)

作者： Cooke, Ryan A. Fahmy, Suhaib A. Univ Warwick Sch Engn Coventry W Midlands England

ISBN: (纸本)9781728199023

FPGA hardware accelerators have recently enjoyed significant attention as platforms for further accelerating computation in the datacenter but they potentially add additional layers of hardware and software interfacing that can further increase communication latency. In this paper, we characterize these overheads for streaming applications where latency can be an important consideration. We examine the latency and throughput characteristics of traditional server-based PCIe connected accelerators, and the more recent approach of network attached FPGA accelerators. We additionally quantify the additional overhead introduced by virtualising accelerators on FPGAs.

关键词： field programmable gate arrays (FPGA)

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On the feasibility of TERO-based true random number generator on Xilinx FPGAs 30

On the feasibility of TERO-based true random number generato...

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30th international conference on field-programmable logic and applications (FPL)

作者： Fujieda, Naoki Aichi Inst Technol Dept Elect & Elect Engn Fac Engn Toyota Aichi Japan

ISBN: (纸本)9781728199023

A True Random Number Generator (TRNG) is an essential component for security applications of FPGAs. Its requirements include small logic area, high throughput, sufficient randomness backed with a mathematical model, and feasibility - ease of implementation. this paper focuses on TRNGs based on a Transition Effect Ring Oscillator (TERO) and presents a three-path configurable TERO (TC-TERO), an improved implementation of TERO that achieves high feasibility with a minimal amount of hardware. According to the evaluation with a Xilinx Artix-7 FPGA, a TC-TERO with a 20-bit configurable parameter only required 40 LUTs. By selecting one of the promising parameters, the proposed TRNG passed AIS-31 Procedure A without post-processing and NIST SP 800-22 with a simple debiasing.

关键词： Random number generation field programmable gate arrays Transition effect ring oscillator AIS-31

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Overview of FPGA and CPLD Device Testing Techniques Based on ATE 3

Overview of FPGA and CPLD Device Testing Techniques Based on...

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3rd IEEE international conference on Circuits and Systems, ICCS 2021

作者： Xie, Weikun Lin, Xiaohui Wang, Houjun Zhang, Kaihong University of Electronic and Technology of China School of Automation Engineering Chengdu China The 58th Research Institute of China Electronics Technology Corporation Testing Center Wuxi China

ISBN: (纸本)9781665412346

Aiming at the test and development of programmable logic devices, this article focuses on the differences in FPGA test configurations from vendors, the differences in CPLD test configurations from vendors, and the differences between FPGA and CPLD device testing. Based on these analysis conclusions, it will play a certain guiding role for subsequent test development and engineering applications. © 2021 IEEE.

关键词： field programmable gate arrays (FPGA)

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Fpga Implementation of Leading Zero Counter for Floating Point Operations

Fpga Implementation of Leading Zero Counter for Floating Poi...

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Artificial Intelligence and Signal Processing (AISP), INDIA, international conference on

作者： Lakshmi Madhumati. G Bhargavi Velivela Hussain Sharif Shaik Baladitya Pasam Dept. Electronics and Communication Engineering Velagapudi Ramakrishna Siddhartha Engineering College Deemed to be University Vijayawada India

ISBN: (数字)9798350350654

ISBN: (纸本)9798350350661

this paper highlights the creation of a leading zero counter designed for floating-point calculations using field programmable gate arrays (FPGAs). A key component of data sketching and floating-point arithmetic is the leading zero counter (LZC). though more and more of these applications are being implemented on FPGAs, current LZC architectures are designed to target application-specific integrated circuits, with certain LZC implementations specifically made for FPGA structures. By effectively recognizing leading zero bits in the exponent portion of floating-point numbers, the design seeks to improve the speed and efficiency of floating-point computations. Better resource usage is achieved by the FPGA-based version by utilizing hardware acceleration techniques and parallel processing, which is essential for high-performance and real-time computing *** designs for various bit widths are given and discussed in further detail. the proposed new LZC is hybrid LZC and the findings indicate that notable decreases in the FPGA resources needed are obtained that reach 11.53 % LUTs saving for 32-bit vectors and 16.66 % LUTs saving for 64-bit vectors and also implements additional 128-bit length with 101 LUTs which reduces 15.833% LUTs.

关键词： Computer architecture Signal processing Parallel processing logic gates Vectors Real-time systems Table lookup field programmable gate arrays Hardware acceleration Floating-point arithmetic

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