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检索条件"任意字段=25th International Conference on Field Programmable Logic and Applications"

共 1845 条记录，以下是141-150 订阅

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Optimized FPGA-Based 16-bits Squarers Using LUTs and a Divide-and-Conquer Approach

Optimized FPGA-Based 16-bits Squarers Using LUTs and a Divid...

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Computing, Internet of things and Microwave Systems (ICCIMS), international conference on

作者： Noureddine Chabini Rachid Beguenane Department of Electrical and Computer Engineering Royal Military College of Canada Kingston ON Canada

ISBN: (数字)9798350351736

ISBN: (纸本)9798350351743

Small squarers are needed in real-life applications. field programmable Gate Arrays (FPGAs), like the modern 7-series Xilinx ones, come with DSP blocks that contain $25\mathrm{x}18$ bits hardwired multipliers. For practical reasons, Look-Up Tables (LUTs) in FPGAs can be used to realize small squarers instead of using these embedded hardwired multipliers. In this paper, we show how divide-and-conquer techniques can be used to perform 8-bits and 9-bits squarers and use these squarers to build 16-bits squarers using LUTs in FPGAs. the proposed 16-bits squarers require small squarers and $8\mathrm{x}8$ bits multipliers. In our first proposed approach, these $8\mathrm{x}8$ bits multipliers are synthesized as LUTs, and are realized using squarers in our second proposed approach. the proposed approaches address both unsigned and signed squarers, and are experimentally tested using Xilinx Artix-7 FPGAs and the Vivado 2020.2 synthesis tool. Experimental results show that the first proposed approach is able to reduce the clock period and the number of LUTs compared to the traditional approach. For the second proposed approach, the clock period has been increased but the area has been reduced. Notice that the speed and the area are two conflicting objectives; increasing the speed leads to increasing the area, and vice versa.

关键词： Microwave integrated circuits logic gates Microwave theory and techniques Table lookup Power dissipation Internet of things Microwave FET integrated circuits field programmable gate arrays Clocks

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A seamless DFT/FFT self-adaptive architecture for embedded radar applications 30

A seamless DFT/FFT self-adaptive architecture for embedded r...

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30th international conference on field-programmable logic and applications (FPL)

作者： Mazuet, Julien Narozny, Michel Dezan, Catherine Diguet, Jean-Philippe Thales LAS France Elancourt France UBO UBS Lab STICC CNRS Brest France

ISBN: (纸本)9781728199023

Radar is one of the domains where adaptability is paramount and algorithms must be adapted to system state. However, most systems include static implementations on FPGA or ASIC to process the massive amount of data from multiple sensors in parallel. the classic approach is to configure hardware logic through registers to switch radar modes, requiring to hardwire all configurations. In embedded systems, FPGA dynamic partial reconfiguration (DPR) is a promising solution to reuse scarce resources. In this paper, we use DPR for radar processing in order to switch between a classic discrete Fourier transform (DFT) sum and a fast Fourier transform (FFT) to enhance Doppler extraction. Our study explores the pros and cons of both methods. Based on these observations, we propose a new architecture and decision method that relies on Radar QoS for enabling an efficient self-adaptive solution. Finally, we provide a case study and a hardware-in-loop simulation with a reconfigurable radar implementation.

关键词： FPGA DPR radar QoS DFT

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TTA-SIMD Soft Core Processors 30

TTA-SIMD Soft Core Processors

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30th international conference on field-programmable logic and applications (FPL)

作者： Tervo, Kati Malik, Samawat Leppanen, Topi Jaaskelainen, Pekka Tampere Univ Tampere Finland

ISBN: (纸本)9781728199023

Soft processors are an important tool in the field programmable Gate Array (FPGA) designer's toolkit, and their Single Instruction Multiple Data (SIMD) organizations are an efficient means to utilize the parallelism of FPGAs. However, the state-of-the-art SIMD processors are hindered by the additional logic complexity resulting from dynamic features. By minimizing such constructs, it is possible to design soft processors that are efficient but still flexible enough to operate within an application domain. To this end, we propose a family of instruction set programmable multi-issue wide SIMD soft cores. the template is based on a highly static Transport Triggered Architecture (TTA) and a design time customizable shuffle unit to minimize inefficient dynamic features while remaining compiler programmable. the cores are evaluated on the PYNQ-Z1 board against the ARM A9 hard processor system with NEON vector extensions. the proposed cores reach up to 2.4x performance improvement over the ARM, can fit up to 1024 bit wide SIMD units onto the relatively small FPGA, while still operating at above 100 MHz. the scalability of TTA enables state of the art vector widths. the multicore scalability of the template is preliminarily tested with a 14-core design on a XCZU9EG FPGA customized for real-time convolutional neural net inference.

关键词： field-programmable Gate Array (FPGA) Transport-Triggered Architecture (TTA) Single Instruction Multiple Data (SIMD)

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Compact and programmable yet High-Performance SoC Architecture for Cryptographic Pairings 30

Compact and Programmable yet High-Performance SoC Architectu...

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30th international conference on field-programmable logic and applications (FPL)

作者： Bahadori, Milad Jarvinen, Kimmo Univ Helsinki Dept Comp Sci Helsinki Finland

ISBN: (纸本)9781728199023

Cryptographic pairings are important primitives for many advanced cryptosystems. Efficient computation of pairings requires the use of several layers of algorithms as well as optimizations in different algorithm and implementation levels. this makes implementing cryptographic pairings a difficult task particularly in hardware. Many existing hardware implementations fix the parameters of the pairing to improve efficiency but this significantly limits the generality and practicality of the solution. In this paper, we present a compact and programmable yet high-performance architecture for programmable system-on-chip platforms designed for efficient computation of different cryptographic pairings. We demonstrate with real hardware that this architecture can compute optimal ate pairings on a Barreto-Naehrig curve with 126-bit security in 2.18 ms in a Xilinx Zynq-7020 device and occupies only about 3200 slices, 36 DSPs, and 18 BRAMs. We also show that the architecture can support different types of pairings via microcode updates and can be implemented on other reprogrammable devices with very minor modifications.

关键词： Cryptographic pairing system-on-chip HW/SW codesign FPGA optimal Ate pairing Barreto-Naehrig curves

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Investigating Impact of Bit-flip Errors in Control Electronics on Quantum Computation

Investigating Impact of Bit-flip Errors in Control Electroni...

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international conference on VLSI Design

作者： Subrata Das Avimita Chatterjee Swaroop Ghosh School of EECS Pennsylvania State University University Park PA USA

ISBN: (数字)9798331522445

ISBN: (纸本)9798331522452

In this paper, we investigate the impact of bit-flip errors in FPGA memories in control electronics on quantum computing systems. FPGA memories are integral in storing the amplitude and phase information pulse envelopes, which are essential for generating quantum gate pulses. However, these memories can incur faults due to physical and environmental stressors such as electromagnetic interference, power fluctuations, and temperature variations and adversarial fault injections, potentially leading to errors in quantum gate operations. To understand how these faults affect quantum computations, we conducted a series of experiments to introduce bit flips into the amplitude (both real and imaginary components) and phase values of quantum pulses using IBM's simulated quantum environments, FakeValencia, FakeManila, and FakeLima. We compare the sensitivity of floating-point and fixed-point representations to these bit-flip errors. the findings reveal that bit flips in the exponent and initial mantissa bits of the real amplitude in floating- point representation cause substantial deviations in quantum gate operations, with TVD increases as high as ~ 200%. Conversely, fixed-point representation shows reduced sensitivity to bit-flips, offering a more robust alternative for certain applications. these in- sights can guide the selection of data representations to enhance the robustness of quantum computing systems from hardware faults.

关键词： Quantum computing Sensitivity Fluctuations logic gates Very large scale integration Reliability engineering Robustness Hardware field programmable gate arrays Resilience

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Novel FPGA-Optimized Stochastic Number Generator for Stochastic Computing 11th

Novel FPGA-Optimized Stochastic Number Generator for Stochas...

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11th international conference on Robotics, Vision, Signal Processing and Power applications, RoViSP 2021

作者： Lee, Yang Yang Abdul Halim, Zaini Ab Wahab, Mohd Nadhir School of Electric and Electronic Engineering Universiti Sains Malaysia Penang Nibong Tebal14300 Malaysia School of Computer Sciences Universiti Sains Malaysia Penang USM11800 Malaysia

ISBN: (纸本)9789811681288

Stochastic computing (SC) is a computing domain that exploits probability mathematics to perform arithmetic operations with a single logic gate. the recent IoT and edge computing trends bring up the SC technology introduced in the 1960s due to its power efficiency and error resilience properties. In SC, a stochastic number generator (SNG) converts binary numbers into stochastic streams via a weighted binary generator (WBG) and linear feedback shift register (LFSR). those application-specific integrated circuit (ASIC) logic gates might not be optimised for the field-programmable gate array (FPGA), causing FPGA resources underutilisation. In contrast, FPGA friendly multiplexer (MUX) could generate stochastic streams directly from binary input with a specialised finite state machine (FSM). However, it is limited on state tracking when the binary resolution expands, bottlenecking the MUX-based SNG's scalability. this paper proposes a novel function block of Weighed Binary Converter (WBC) to port the traditional LFSR to MUX, eliminating FSM bottlenecking and improving MUX SNG's scalability than WBG SNG in FPGA. the designs are synthesised with Xilinx Vivado HLS targeted at Z7010 FPGA SoC. the result shows that WBC enables 50% resource reduction on 4-bit MUX SNG and 62.5% bus width reduction on 8-bit MUX SNG, speeding up the logic setup time by 15.1% and 7.3%, respectively, compared to the ASIC logic transcoded WBG SNG. © 2022, the Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.

关键词： logic gates

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Using Novel Configuration Techniques for Accelerated FPGA Aging 30

Using Novel Configuration Techniques for Accelerated FPGA Ag...

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30th international conference on field-programmable logic and applications (FPL)

作者： Gaskin, Tanner Cook, Hayden Stirk, Wesley Lucas, Robert Goeders, Jeffrey Hutchings, Brad Brigham Young Univ Dept Elect & Comp Engn Provo UT 84602 USA

ISBN: (纸本)9781728199023

In this work we demonstrate a novel method of accelerating FPGA aging by configuring the FPGA to implement thousands of short circuits, resulting in high on-chip currents and temperatures. three ring oscillators are placed across the chip and are used to characterize the operating frequency of the FPGA fabric. Over the course of several weeks of running the short circuits, with daily characterization of the FPGA performance, we measured a decrease in FPGA frequency greater than 5%. After aging, the FPGA part was repeatedly characterized during a two week idle period. Results indicated that the slowdown did not change, and the aging appeared to be permanent. In addition, we demonstrated that this aging could be induced in a non-uniform manner. In our experiments, the short circuits were all placed in the lower two-thirds of the chip, and one of the characterization ring oscillators was placed at the top of the chip, outside of the region with the short circuits. the fabric at this location exhibited a 1.36% slowdown, only one-quarter the slowdown measured in the targeted region.

关键词： field programmable gate arrays (FPGA)

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TD3lite: FPGA Acceleration of Reinforcement Learning with Structural and Representation Optimizations

TD3lite: FPGA Acceleration of Reinforcement Learning with St...

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international conference on field programmable logic and applications

作者： Chan-Wei Hu Jiang Hu Sunil P. Khatri Department of Computer Science and Engineering Texas A&M University Department of Electrical and Computer Engineering Texas A&M University

Reinforcement learning (RL) is an effective and increasingly popular machine learning approach for optimization and decision-making. However, modern reinforcement learning techniques, such as deep Q-learning, often require neural network inference and training, and therefore are computationally expensive. For example, Twin-Delay Deep Deterministic Policy Gradient (TD3), a state-of-the-art RL technique, uses as many as 6 neural networks. In this work, we study the FPGA-based acceleration of TD3. To address the resource and computational overhead due to inference and training of the multiple neural networks of TD3, we propose TD3lite, an integrated approach consisting of a network sharing technique combined with bitwidth-optimized block floating-point arithmetic. TD3lite is evaluated on several robotic benchmarks with continuous state and action spaces. With only 5.7% learning performance degradation, TD3lite achieves 21 ×and 8 ×speedup compared to CPU and GPU implementations, respectively. Its energy efficiency is 26 ×of the GPU implementation. Moreover, it utilizes ~ 25 - 40% fewer FPGA resources compared to a conventional sinale-precision floating-point representation of TD3.

关键词： Training Q-learning Neural networks Graphics processing units Benchmark testing Resource management field programmable gate arrays

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SpaceFibre Multi-Lane Routing Switch IP 9

SpaceFibre Multi-Lane Routing Switch IP

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9th international SpaceWire and SpaceFibre conference, ISC 2022

作者： Florit, Albert Ferrer Villafranca, Alberto Gonzalez Casas, Marti Farras Parkes, Steve STAR-Barcelona SL Sant Cugat Del Valles Barcelona Spain STAR-Dundee Dundee United Kingdom

ISBN: (纸本)9780995453029

SpaceFibre (ECSS-E-ST-50-11C) is a very high-performance, high-reliability and high-availability network technology specifically designed to meet the needs of space applications. It provides point-to-point and networked interconnections at Gigabit rates with Quality of Service (QoS) and Fault Detection, Isolation and Recovery (FDIR). SpaceFibre has been designed as a replacement of SpaceWire (ECSS-E-ST-50-12C) - it is backwards compatible with SpaceWire at the packet level - for next-generation space missions where very high throughput is required. SpaceFibre provides up to 6.25 Gbit/s per lane, with multi-lane allowing to reach up to 16 times the speed of a single lane. In this work we present the SpaceFibre Multi-Lane Routing Switch IP Core developed by STAR-Dundee and its subsidiary STAR-Barcelona. this IP provides a highly flexible router comprising a number of ports and a fully configurable, non-blocking, high performance, routing switch matrix. the internal ports use AXI4-Stream protocol, and the external ports can implement SpaceFibre or SpaceWire interfaces. the SpaceWire ports include additional bridging logic for efficient interconnection between SpaceWire and SpaceFibre equipment. the core logic of the IP is technology independent but has been optimised to be easily implemented in radiation tolerant FPGAs. the routing switch is fully compliant with all layers of the SpaceFibre standard, supporting up to 64 virtual networks and 256 broadcast channels. Among other features, it implements network time synchronisation, packet time-outs, and automatic translation between SpaceFibre broadcast messages and SpaceWire broadcast codes (SpaceWire Time-Codes or Interrupts). With up to 8 lanes per SpaceFibre interface, raw link rates of 50Gbps per port can be achieved. the multi-lane routing Switch Ip Core is implemented in the STAR-Tiger Routing Switch of the Hi-SIDE project. © 2022 European Space Agency.

关键词： field programmable gate arrays (FPGA)

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Towards Automated FPGA Compilation of Spiking Neural Networks

Towards Automated FPGA Compilation of Spiking Neural Network...

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IEEE international conference on Artificial Intelligence Circuits and Systems (AICAS)

作者： Ayan Shymyrbay Mohammed E. Fouda Ahmed Eltawil Department of ECE CEMSE Division King Abdullah University of Science and Technology Thuwal Saudi Arabia Rain Neuromorphics Inc. San Francisco CA USA

ISBN: (数字)9798350383638

ISBN: (纸本)9798350383645

Edge computing and the Internet of things (IoT) have created a growing demand for low-cost and low-power field programmable gate arrays (FPGAs) to facilitate rapid and efficient processing. At the same time, spiking neural networks (SNNs) have gained popularity for their capacity to replicate biological processes and efficiently handle temporal data, making them a favorable choice in various IoT applications. However, designers must possess a comprehensive knowledge of FPGA architecture and programming methodologies to fully exploit the potential of FPGAs for SNN implementations. In this work, we propose SpiComp framework aiming to automate the implementation of SNNs on FPGAs, leveraging their reconfigurable nature and high efficiency without requiring domain expertise. Results show that the SNN implementations produced by the framework achieve high throughput and have a small energy footprint compared to other implementations in the literature while providing design automation.

关键词： Design automation Circuits and systems Spiking neural networks Computer architecture logic gates Programming throughput

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