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检索条件"任意字段=25th International Conference on Field Programmable Logic and Applications"

共 1846 条记录，以下是151-160 订阅

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Towards Automated FPGA Compilation of Spiking Neural Networks

Towards Automated FPGA Compilation of Spiking Neural Network...

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IEEE international conference on Artificial Intelligence Circuits and Systems (AICAS)

作者： Ayan Shymyrbay Mohammed E. Fouda Ahmed Eltawil Department of ECE CEMSE Division King Abdullah University of Science and Technology Thuwal Saudi Arabia Rain Neuromorphics Inc. San Francisco CA USA

ISBN: (数字)9798350383638

ISBN: (纸本)9798350383645

Edge computing and the Internet of things (IoT) have created a growing demand for low-cost and low-power field programmable gate arrays (FPGAs) to facilitate rapid and efficient processing. At the same time, spiking neural networks (SNNs) have gained popularity for their capacity to replicate biological processes and efficiently handle temporal data, making them a favorable choice in various IoT applications. However, designers must possess a comprehensive knowledge of FPGA architecture and programming methodologies to fully exploit the potential of FPGAs for SNN implementations. In this work, we propose SpiComp framework aiming to automate the implementation of SNNs on FPGAs, leveraging their reconfigurable nature and high efficiency without requiring domain expertise. Results show that the SNN implementations produced by the framework achieve high throughput and have a small energy footprint compared to other implementations in the literature while providing design automation.

关键词： Design automation Circuits and systems Spiking neural networks Computer architecture logic gates Programming throughput

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Accelerated Edge Detection Algorithm for High-Speed applications 9

Accelerated Edge Detection Algorithm for High-Speed Applicat...

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9th international Japan-Africa conference on Electronics, Communications, and Computations, JAC-ECC 2021

作者： Saad, Aya Rafat, Khloud Soltan, Ahmed Darweesh, M. Saeed Nile University School of Engineering and Applied Sciences Giza12588 Egypt Nile University Giza12588 Egypt Nile University Giza12588 Egypt

ISBN: (纸本)9781665482929

Digital Image Processing (DIP) is a growing field for various applications, such as autonomous vehicles and video surveillance. To improve the performance of DIP systems, image processing algorithms are implemented in hardware rather than software. the idea here is primarily to get a faster system than software imaging or other alternative hardware. field-programmable gate arrays (FPGAs) have the advantages of parallel processing, low cost, and low power consumption. these semiconductor devices contain many logic blocks that can be programmed to perform everything from basic digital gate-level technology to complex image processing algorithms. this paper provides an enhancement pipeline system architecture using AXI interface to implement image processing algorithms such as Sobel edge detection and mean filters on the Zybo z7 Zynq 7010 board using Verilog HDL language. the system is implemented in a 512×512 image that takes 0.009ms in the processing system. © 2021 IEEE.

关键词： field programmable gate arrays (FPGA)

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logicNets: Co-Designed Neural Networks and Circuits for Extreme-throughput applications 30

LogicNets: Co-Designed Neural Networks and Circuits for Extr...

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30th international conference on field-programmable logic and applications (FPL)

作者： Umuroglu, Yaman Akhauri, Yash Fraser, Nicholas J. Blott, Michaela Xilinx Res Labs Dublin Ireland

ISBN: (纸本)9781728199023

Deployment of deep neural networks for applications that require very high throughput or extremely low latency is a severe computational challenge, further exacerbated by inefficiencies in mapping the computation to hardware. We present a novel method for designing neural network topologies that directly map to a highly efficient FPGA implementation. By exploiting the equivalence of artificial neurons with quantized inputs/outputs and truth tables, we can train quantized neural networks that can be directly converted to a netlist of truth tables, and subsequently deployed as a highly pipelinable, massively parallel FPGA circuit. However, the neural network topology requires careful consideration since the hardware cost of truth tables grows exponentially with neuron fan-in. To obtain smaller networks where the whole netlist can be placed-and-routed onto a single FPGA, we derive a fan-in driven hardware cost model to guide topology design, and combine high sparsity with few-bit activation quantization to limit the neuron fan-in. We evaluate our approach on two tasks with very high intrinsic throughput requirements in high-energy physics and network intrusion detection. We show that the combination of sparsity and few-bit activation quantization results in high-speed circuits with small logic depth and low LUT cost, demonstrating competitive accuracy with less than 15 ns of inference latency and throughput in the hundreds of millions of inferences per second.

关键词： deep learning fpga logic synthesis machine learning network security quantization quantized neural network sparsity

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Formal Methods of FPGA Project Verification Flow 11

Formal Methods of FPGA Project Verification Flow

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11th IEEE international conference on Intelligent Data Acquisition and Advanced Computing Systems - Technology and applications (IDAACS)

作者： Naumenko, Serhii Moskalets, Viktoriia Odarushchenko, Oleg Odarushchenko, Elena Peschanenko, Volodymyr Degtyareva, Larysa Letychevskyi, Oleksandr Poltava State Agr Acad Poltava Ukraine Rad LLC Kropyvnytskiy Ukraine Kherson State Univ Kherson Ukraine NAS Ukraine VM Glushkov Inst Cybernet Kiev Ukraine

ISBN: (纸本)9781665426053

FPGA technology for developing safety-based PLCs for industrial applications (for example NPP I&C) became more popular. One of the main part of FPGA-based I&C system lifecycle is verification. FPGA Project Verification main stages are described. Verification influence on product development time, cost and quality are described. the article presents a new approach to performing the functional testing stage. this approach is based on the use of formal algebraic methods. the main advantage of using this approach is the increase in testing efficiency due to the use of the procedure for automatic generation of test cases. More than 10 years' experience of verification approaches of Radics LLC verification team is presented.

关键词： I&C systems PLC - programmable logic controller NPP - nuclear power plant verification EDD - electronic detailed design FPGA - field-programmable gate array algebraic modeling formal verification methods

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LOTTA: An FPGA-based Low-Power Temporal Convolutional Network Hardware Accelerator

LOTTA: An FPGA-based Low-Power Temporal Convolutional Networ...

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IEEE international SOC conference

作者： Fabian Kreß Alexey Serdyuk Denis Kobsar Tim Hotfilter Julian Hoefer Tanja Harbaum Jürgen Becker Karlsruhe Institute of Technology Karlsruhe Germany

ISBN: (数字)9798350377569

ISBN: (纸本)9798350377576

Deploying artificial intelligence (AI) in the Internet of things (IoT) is primarily limited by energy consumption. Optimized hardware architectures are therefore essential to meet the requirements of such applications. In this paper, we present LOTTA, a novel, low-power hardware accelerator for Temporal Convolutional Networks (TCNs) specifically designed for use in IoT applications. LOTTA is designed to efficiently utilize FPGA resources and can be configured at runtime via an SPI interface, providing high flexibility for different workloads. It also provides a QSPI interface to expand the weight memory and thus supports TCN network architectures that exceed the FPGA’s internal memory. In addition, a hardware-aware TCN hyperparameter search is proposed to find a TCN architecture that is well adapted to the hardware. Our evaluations on a low-power Lattice iCE40 UP5K FPGA show that LOTTA requires only 3,990 logic cells and offers a high performance of 0.12 GOP/s. Furthermore, our measurements reveal a low power consumption of 27.28 mW including 4 Mbit external non-volatile memory, which consequently underlines that our accelerator design enables the use of TCNs in IoT devices with highly constrained power consumption.

关键词： Power demand Runtime Power measurement Speech recognition System-on-chip Internet of things Convolutional neural networks Artificial intelligence field programmable gate arrays Hardware acceleration

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A Domain-Specific Architecture for Accelerating Sparse Matrix Vector Multiplication on FPGAs 30

A Domain-Specific Architecture for Accelerating Sparse Matri...

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30th international conference on field-programmable logic and applications (FPL)

作者： Jain, Abhishek Kumar Omidian, Hossein Fraisse, Henri Benipal, Mansimran Liu, Lisa Gaitonde, Dinesh Xilinx Inc San Jose CA 95124 USA

ISBN: (纸本)9781728199023

FPGAs allow custom memory hierarchy and flexible data movement with highly fine-grained control. these capabilities are critical for building high performance and energy efficient domain-specific architectures (DSAs), especially for workloads with irregular memory access and data-dependent communication patterns. Sparse linear algebra operations, especially sparse matrix vector multiplication (SpMV), are examples of such workloads and are becoming important due to their use in numerous areas of science and engineering. Existing FPGA-based DSAs for SpMV do not allow customization through plug and play of the building blocks. For example, most of these DSAs require switching network/crossbar architecture as a building block for routing matrix data to banked vector memory blocks. In this paper, we first present an approach where a custom network is built using simple blocks arranged in a regular fashion to exploit low-level architecture details. Further, we make use of this network to replace expensive crossbars employed in GEMX SpMV engine and develop an end-to-end tool-flow around mixed IP approach (HLS/RTL). Due to the modularity of our design, our tool-flow allows us to insert an additional block in the design to guarantee zero-stall from the accumulation stage. On Alveo U200, we report performance numbers of up to 4.4 GFLOPS (92% peak bandwidth utilization) using our accelerator (attached with one DDR4).

关键词： field programmable gate arrays (FPGA)

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FP-Stereo: Hardware-Efficient Stereo Vision for Embedded applications 30

FP-Stereo: Hardware-Efficient Stereo Vision for Embedded App...

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30th international conference on field-programmable logic and applications (FPL)

作者： Zhao, Jieru Liang, Tingyuan Feng, Liang Ding, Wenchao Sinha, Sharad Zhang, Wei Shen, Shaojie Hong Kong Univ Sci & Technol Hong Kong Peoples R China Alibaba Grp Hangzhou Peoples R China India Inst Technol Goa Ponda Goa India

ISBN: (纸本)9781728199023

Fast and accurate depth estimation, or stereo matching, is essential in embedded stereo vision systems, requiring substantial design effort to achieve an appropriate balance among accuracy, speed and hardware cost. To reduce the design effort and achieve the right balance, we propose FP-Stereo for building high-performance stereo matching pipelines on FPGAs automatically. FP-Stereo consists of an open-source hardware-efficient library, allowing designers to obtain the desired implementation instantly. Diverse methods are supported in our library for each stage of the stereo matching pipeline and a series of techniques are developed to exploit the parallelism and reduce the resource overhead. To improve the usability, FP-Stereo can generate synthesizable C code of the FPGA accelerator with our optimized HLS templates automatically. To guide users for the right design choice meeting specific application requirements, detailed comparisons are performed on various configurations of our library to investigate the accuracy/speed/cost trade-off. Experimental results also show that FP-Stereo outperforms the state-of-the-art FPGA design from all aspects, including 6.08% lower error, 2x faster speed, 30% less resource usage and 40% less energy consumption. Compared to GPU designs, FP-Stereo achieves the same accuracy at a competitive speed while consuming much less energy.

关键词： field programmable gate arrays (FPGA)

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A High -Performance Out -of-Order Soft Processor Without Register Renaming 30

A High -Performance Out -of-Order Soft Processor Without Reg...

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30th international conference on field-programmable logic and applications (FPL)

作者： Mitsuno, Satoshi Kadomoto, Junichiro Koizumi, Toru Shioya, Ryota Irie, Hidetsugu Sakai, Shuichi Univ Tokyo Tokyo Japan

ISBN: (纸本)9781728199023

Owing to the growth of FPGA-based systems and the increasing complexity of applications, the demand for highperformance soft processors in FPGAs has increased. the performance of processors is enhanced through out-of-order (000) superscalar execution using a register renaming mechanism. However, the register renaming mechanism has two problems. First, it requires a register mapping table (RMT), which usually comprises a RAM with a large number of ports. A multi-port RAM is not suitable for an FPGA. Second, register renaming complicates recovery mechanisms for exceptions, such as branch mispredictions. these problems increase the usage of resources and hinder the improvement of performance. Recently, the STRAIGHT architecture was proposed to solve these problems. STRAIGHT has a unique instruction format and enables OoO execution without register renaming. this approach eliminates the RMT and makes the recovery operation more efficient. In this study, we demonstrate a high-performance OoO STRAIGHT soft processor by implementing several mechanisms for adopting the STRAIGHT architecture and fabricate the first STRAIGHT processor capable of executing practical complex programs. Compared to a state-of-the-art OoO soft processor, our processor consumes approximately 17% fewer LUTs and 10% fewer FlipFlops and achieves 15% higher performance in CoreMark, which is a standard benchmark.

关键词： field programmable gate arrays (FPGA)

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Exploring FPGA Optimizations in OpenCL for Breadth-First Search on Sparse Graph Datasets 30

Exploring FPGA Optimizations in OpenCL for Breadth-First Sea...

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30th international conference on field-programmable logic and applications (FPL)

作者： Gondhalekar, Atharva Feng, Wu-Chun Virginia Tech Dept ECE Blacksburg VA 24061 USA Virginia Tech Dept CS & ECE Blacksburg VA USA

ISBN: (纸本)9781728199023

Breath-first search (BFS) is a fundamental building block in many graph-based applications, but it is difficult to optimize due to its irregular memory-access patterns. Prior work, based on hardware description languages and high-level synthesis, address the memory-access bottleneck by using techniques such as edge-centric traversal, data alignment, and compute-unit replication. While these optimizations work well for dense graphs, they are ineffective for sparse graphs due to kernel launch overhead and poor workload distribution across processing elements. thus, to complement this prior work, we present and evaluate optimizations in OpenCL for BFS on sparse graphs. Specifically, we explore application-specific and architecture-aware optimizations aimed at mitigating the irregular global-memory access bottleneck in sparse graphs. Our kernel design considers factors such as data structure (i.e., queue vs. array), number of memory banks, and kernel launch configuration. Across a diverse set of sparse graphs, our optimizations deliver a 5.7x to 22.3x speedup on Stratix 10 FPGA when compared to a state-of-the-art OpenCL implementation for FPGA.

关键词： FPGA BFS OpenCL HLS sparse graphs dense graphs graph traversal irregular applications

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Development of Operation Technology Network for Process Flow Control Loop Components

Development of Operation Technology Network for Process Flow...

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international conference on Electrical, Control and Instrumentation Engineering (ICECIE)

作者： Meera A Khandekar Sudhir Agashe Raunak Pawar Instrumentation and Control Engineering COEP Technological University Pune India Instrumentation and Control Engg COEP Technological University Pune India

ISBN: (纸本)9781665480772

Any industrial plant includes many operation areas. these areas are controlled using different controllers like Pro-grammable logic Controller and Distributed Control System. To run these operations proper networking is required. In industry OT networking is always challenging as variety of instruments, controllers are involved. In this paper programmable logic Controller to Distributed Control system communication is im-plemented. Flow loop is interfaced to Micrologix 1400 PLC. Likewise we have 14 local programmable logic Controllers. Using Modbus TCP/IP communication all field devices data is available to common network. Modbus TCP gateway is configured to communicate, field devices real time data to serial card of DeltaV host system. Real time data from field devices is available to DeltaV DCS workstations. Note to Practitioner-this paper was motivated by the challenges of networking operational technology and IT technology in any industry. In industry variety of field devices are used to run processes or machines. We can classify field devices as Digital Input, Digital Output, Analog Input, and Analog Output. Even controllers like Distributed Control Systems (DCS) and programmable logic Controllers (PLC) are offered by a variety of manufacturers. We need to configure field devices to controllers through input and output modules. DCS system supports applications like insight and AMS. We have to monitor the performance of the flow loop, which is operated through local PLC-Micrologix 1400. Modbus TCP/IP communication is demonstrated for communication between PLC-Micrologix 1400 and DeltaV DCS. For each field device registers have been mapped. Modbus gateway needs to configure with PLC-Micrologix 1400 IP address. Data sets are created in DeltaV for the field devices. Using the Delat V process historian, we can monitor trends for all parameters. Further, using the DeltaV Insight application, we can monitor the performance of the closed-loop system.

关键词： Industries Performance evaluation Instruments programmable logic devices Decentralized control TCPIP logic gates

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