检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

1,813 篇 会议
29 篇 期刊文献
5 册 图书

馆藏范围

1,847 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

1,202 篇 工学
- 1,019 篇 计算机科学与技术...
- 707 篇 软件工程
- 388 篇 电气工程
- 186 篇 电子科学与技术（可...
- 62 篇 信息与通信工程
- 60 篇 控制科学与工程
- 26 篇 机械工程
- 26 篇 仪器科学与技术
- 25 篇 动力工程及工程热...
- 24 篇 建筑学
- 16 篇 土木工程
- 14 篇 生物工程
- 11 篇 核科学与技术
- 10 篇 材料科学与工程（可...
- 9 篇 光学工程
- 8 篇 生物医学工程（可授...
- 8 篇 安全科学与工程
- 6 篇 化学工程与技术
- 6 篇 交通运输工程
146 篇 理学
- 97 篇 数学
- 33 篇 物理学
- 16 篇 生物学
- 14 篇 系统科学
- 10 篇 统计学（可授理学、...
- 6 篇 化学
52 篇 管理学
- 39 篇 管理科学与工程(可...
- 17 篇 工商管理
- 15 篇 图书情报与档案管...
14 篇 法学
- 12 篇 社会学
9 篇 经济学
- 9 篇 应用经济学
8 篇 医学
6 篇 农学
4 篇 军事学
2 篇 教育学

主题

816 篇 field programmab...
670 篇 field programmab...
271 篇 hardware
154 篇 computer archite...
119 篇 logic gates
111 篇 table lookup
94 篇 clocks
83 篇 throughput
78 篇 random access me...
72 篇 routing
71 篇 acceleration
71 篇 software
66 篇 optimization
63 篇 kernel
61 篇 delays
52 篇 registers
52 篇 logic
49 篇 switches
46 篇 algorithm design...
45 篇 computational mo...

机构

15 篇 univ toronto dep...
9 篇 department of co...
9 篇 imperial coll lo...
8 篇 ecole polytech f...
7 篇 univ british col...
7 篇 school of comput...
7 篇 brigham young un...
7 篇 imperial coll lo...
7 篇 tokyo inst techn...
6 篇 univ tsukuba tsu...
6 篇 university of ch...
6 篇 department of el...
6 篇 univ warwick sch...
6 篇 xilinx inc san j...
5 篇 univ manchester ...
5 篇 department of el...
5 篇 univ toronto dep...
5 篇 swiss fed inst t...
5 篇 xilinx inc 2100 ...
5 篇 altera corp san ...

作者

33 篇 luk wayne
21 篇 maruyama tsutomu
16 篇 wayne luk
16 篇 koch dirk
12 篇 wilton steven j....
12 篇 betz vaughn
12 篇 ienne paolo
11 篇 fahmy suhaib a.
11 篇 cheung peter y. ...
10 篇 vaughn betz
9 篇 constantinides g...
8 篇 suhaib a. fahmy
8 篇 prasanna viktor ...
8 篇 chow paul
8 篇 glesner manfred
8 篇 amano hideharu
8 篇 akash kumar
7 篇 kapre nachiket
7 篇 alonso gustavo
7 篇 hutchings brad

语言

1,838 篇 英文
9 篇 其他

检索条件"任意字段=25th International Conference on Field Programmable Logic and Applications"

共 1847 条记录，以下是1611-1620 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Artificial neural networks processor – A hardware implementation using a FPGA 14th

Artificial neural networks processor – A hardware implement...

引用

14th international conference on field programmable logic and applications, FPL 2004

作者： Ferreira, Pedro Ribeiro, Pedro Antunes, Ana Dias, Fernando Morgado Escola Superior de Tecnologia de Setúbal do Instituto Politécnico de Setúbal Departamento de Engenharia Electrotécnica Campus do IPS Estefanilha Setúbal2914-508 Portugal

ISBN: (纸本)3540229892

Several implementations of Artificial Neural Networks have been reported in scientific papers. Nevertheless, these implementations do not allow the direct use of off-line trained networks because of the much lower precision when compared with the software solutions where they are prepared or modifications in the activation function. In the present work a hardware solution called Artificial Neural Network Processor, using a FPGA, fits the requirements for a direct implementation of Feedforward Neural Networks, because of the high resolution and accurate activation function that were obtained. the resulting hardware solution is tested with data from a real system to confirm that it can correctly implement the models prepared off-line with MATLAB. © Springer-Verlag Berlin Heidelberg 2004.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

IP generation for an FPGA-based audio DAC sigma-delta converter

IP generation for an FPGA-based audio DAC sigma-delta conver...

引用

14th international conference on field programmable logic and applications, FPL 2004

作者： Ludewig, Ralf Soffke, Oliver Zipf, Peter Glesner, Manfred Pun, Kong Pang Tsoi, Kuen Hung Lee, Kin Hong Leong, Philip Institute of Microelectronic Systems Darmstadt University of Technology Germany Department of Computer Science and Engineering Chinese University of Hong Kong Shatin NT Hong Kong

ISBN: (纸本)3540229892

In this paper we describe a parameterizable FPGA-based implementation of a sigma-delta converter used in a 96kHz audio DAC. From specifications of the converter’s input bitwidth and data sampling frequency, VHDL generic parameters are used to automatically generate the required design. the resulting implementation is optimized to use the minimum internal wordlength and number of stages. We prototyped the converter on an FPGA board for verification purposes and the results are presented. © Springer-Verlag Berlin Heidelberg 2004.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

An instance-specific hardware algorithm for finding a maximum clique

An instance-specific hardware algorithm for finding a maximu...

引用

14th international conference on field programmable logic and applications, FPL 2004

作者： Wakabayashi, Shin’Ichi Kikuchi, Kenji Hiroshima City University 3-4-1 Ozuka-higashi Asaminami-ku Hiroshima731-3194 Japan

ISBN: (纸本)3540229892

this paper presents a hardware algorithm for finding a maximum clique of a given graph, and shows experimental results of the proposed algorithm running on an FPGA. the proposed algorithm is constructed according to a given instance of graph, and can find a maximum clique efficiently based on branch and bound search. the proposed algorithm is designed to be implemented on FPGAs, and realizes an efficient branch and bound search with parallel and pipeline processing. Experimental results showed that, compared with the software solver, the proposed algorithm produced a maximum clique in a very shorter running time even if the time for circuit synthesis and configuration of FPGA was taken into account. © Springer-Verlag Berlin Heidelberg 2004.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

On optimal irregular switch box designs

On optimal irregular switch box designs

引用

14th international conference on field programmable logic and applications, FPL 2004

作者： Fan, Hongbing Wu, Yu-Liang Cheung, Chak-Chung Liu, Jiping The University of Lethbridge LethbridgeABT1K 3M4 Canada The Chinese University of Hong Kong Shatin NT Hong Kong Department of Computing Imperial College London United Kingdom

ISBN: (纸本)3540229892

In this paper, we develop a unified theory in analyzing optimal switch box design problems, particularly for the unsolved irregular cases, where different pin counts are allowed on different sides. the results drawn from our system of linear Diophantine equations based formulation turn out to be general. We prove that the divideand-conquer (reduction) design methodology can also be applied to the irregular cases. Namely, an optimal arbitrarily large irregular or regular switch box can be obtained by combining small prime switch boxes, which largely reduces the design complexity. We revise the known VPR router for our experiments and show that the design optimality of switch boxes does pay off. © Springer-Verlag Berlin Heidelberg 2004.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

Monte Carlo radiative heat transfer simulation on a reconfigurable computer

Monte Carlo radiative heat transfer simulation on a reconfig...

引用

14th international conference on field programmable logic and applications, FPL 2004

作者： Gokhale, Maya Frigo, Janette Ahrens, Christine Tripp, Justin L. Minnich, Ron Los Alamos National Laboratory United States

ISBN: (纸本)3540229892

Recently, the appearance of very large (3 – 10M gate) FPGAs with embedded arithmetic units has opened the door to the possibility of floating point computation on these devices. While previous researchers have described peak performance or kernel matrix operations, there is as yet relatively little experience with mapping an application-specific floating point loop onto FPGAs. In this work, we port a supercomputer application benchmark onto Xilinx Virtex II and Virtex II Pro FPGAs and compare performance with three Pentium IV Xeon microprocessors. Our results show that this application-specific pipeline, with 12 multiply, 10 add/subtract, one divide, and two compare modules of single precision floating point data type, shows speed up of 10.37×.We analyze the tradeoffs between hardware and software to characterize the algorithms that will perform well on current and future FPGA architectures. © Springer-Verlag Berlin Heidelberg 2004.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

Automating optimized table-with-polynomial function evaluation for FPGAs

Automating optimized table-with-polynomial function evaluati...

引用

14th international conference on field programmable logic and applications, FPL 2004

作者： Lee, Dong-U Mencer, Oskar Pearce, David J. Luk, Wayne Department of Computing Imperial College London United Kingdom

ISBN: (纸本)3540229892

Function evaluation is at the core of many compute-intensive applications which perform well on reconfigurable ***, in order to implement function evaluation efficiently, the FPGA programmer has to choose between a multitude of function evaluation methods such as table lookup, polynomial approximation, or table lookup combined with polynomial approximation. In this paper, we present a methodology and a partially automated implementation to select the best function evaluation hardware for a given function, accuracy requirement, technology mapping and optimization metrics, such as area, throughput and latency. the automation of function evaluation unit design is combined with ASC,A Stream Compiler, for FPGAs. On the algorithmic side, MATLAB designs approximation algorithms with polynomial coefficients and minimizes bitwidths. On the hardware implementation side, ASC provides partially automated design space exploration. We illustrate our approach for sin(x), log(1+x) and 2x with a selection of graphs that characterize the design space with various dimensions, including accuracy, precision and function evaluation method. We also demonstrate design space exploration by implementing more than 400 distinct designs. © Springer-Verlag Berlin Heidelberg 2004.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

A framework for energy efficient design of multi-rate applications using hybrid reconfigurable systems

A framework for energy efficient design of multi-rate applic...

引用

14th international conference on field programmable logic and applications, FPL 2004

作者： Mohanty, Sumit Prasanna, Viktor K. University of Southern California CA United States

ISBN: (纸本)3540229892

Hybrid reconfigurable systems integrate DSPs and general purpose processors with an FPGA fabric. these systems may support features such as efficient start-up and shut-down, dynamic voltage scaling, and reconfiguration, that are exploited for energy-efficient application design. Duty cycle is the proportion of time during which a system is operated. Multi-rate applications consist of tasks that execute at different rates. Designing an energy-efficient hybrid reconfigurable system with duty cycle specification that implements a multi-rate application using devices with multiple operating states presents several challenges such as modeling, rapid performance estimation, and efficient design space exploration. We present a design framework that addresses these challenges. Using our framework, we illustrate the design of two energy efficient systems: automated target detection and adaptive beamforming. © Springer-Verlag Berlin Heidelberg 2004.

关键词： Voltage scaling

来源：评论

学校读者我要写书评

暂无评论

Comparative study of SRT-dividers in FPGA

Comparative study of SRT-dividers in FPGA

引用

14th international conference on field programmable logic and applications, FPL 2004

作者： Sutter, Gustavo Bioul, Gery Deschamps, Jean-Pierre School of Engineering Universidad Autonoma de Madrid Spain UNC-Tandil UFASTA-Mar del Plata Argentina Dept. Eng. Electrònica Elèctrica i Automàtica Universitat Rovira i Virgili Tarragona Spain

ISBN: (纸本)3540229892

this paper describes different implementations of dividers on FPGA. Many division algorithms have been adapted for FPGA technology;nevertheless the peculiar characteristics of re-configurable hardware devices deserve special attention to ensure efficient implementations. this paper presents comparative analyses of implementations targeting Virtex and Virtex II FPGA technology. With respect to the algorithms, selected comparison criteria are operand widths, remainder representations and radix options. At the implementation level, latency, throughput, and area consumption have been traded-off within array, pipelined and sequential options;the results have been compared with previous ones. Area and speed improvements have been obtained thanks to careful implementation techniques. With respect to non-restoring implementations, significant delay improvements - up to 42% - have been achieved. © Springer-Verlag Berlin Heidelberg 2004.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

SoftSONIC: A customisable modular platform for video applications

SoftSONIC: A customisable modular platform for video applica...

引用

14th international conference on field programmable logic and applications, FPL 2004

作者： Rissa, Tero Cheung, Peter Y. K. Luk, Wayne Department of Computing Imperial College London United Kingdom Department of Electrical and Electronic Engineering Imperial College London United Kingdom

ISBN: (纸本)3540229892

this paper presents the Customisable Modular Platform (CMP) approach. the aim is to accelerate FPGA application development by raising the level of abstraction and facilitating design reuse. the solution is based on network of Nodes, communicating using packetbased protocol. the approach is illustrated using SoftSONIC, a CMP for video applications. Our approach promotes modularity and design reuse by having multiple interoperable layers of design abstraction, while supporting advanced development and verification methods such as mixedabstraction execution and efficient system-level simulation based on Transaction Level Modelling. the platform provides domain-specific abstractions and customisations of various elements such as communication protocols and topology, enabling exploitation of data locality and fineand coarse-grain parallelism. the benefits of our approach is demonstrated using SoftSONIC for development of several real-time HDTV video processing applications. © Springer-Verlag Berlin Heidelberg 2004.

关键词： Abstracting

来源：评论

学校读者我要写书评

暂无评论

A methodology for energy efficient FPGA designs using malleable algorithms 14th

A methodology for energy efficient FPGA designs using mallea...

引用

14th international conference on field programmable logic and applications, FPL 2004

作者： Ou, Jingzhao Prasanna, Viktor K. Department of Electrical Engineering University of Southern California Los AngelesCA90089-2560 United States

ISBN: (纸本)3540229892

A recent trend towards integrating FPGAs with many heterogeneous components, such as memory systems, dedicated multipliers, etc., has made them an attractive option for implementing many embedded systems. Paradoxically, the integration that makes modern FPGAs an attractive computing substrate also makes the development of energy efficient FPGA designs very challenging in practice. this is due to the many alternatives available for implementing a desired functionality and a lack of high-level models of FPGA architectures that can accurately capture the energy dissipation behavior of alternatives. To address these issues, we propose a methodology for energy efficient FPGA designs using malleable algorithms. Malleable algorithms are used to expose the architecture platform aware specifications of alternate implementations of the desired functionalities. Our methodology consists of three major design steps: domain-specific energy performance modeling, development of malleable algorithms, and system level optimization. Energy efficient designs are realized through close interaction among these three design steps. To illustrate the proposed design methodology and demonstrate the benefits of designing using malleable algorithms, we present the development of a beamforming application through a high-levelMAT-LAB/Simulink based FPGA design tool developed by us. By tuning the design knobs exposed by malleable algorithms, the design of the beamforming application identified through system-level optimization achieves up to 30% energy reduction compared with other designs considered in our experiments. © Springer-Verlag Berlin Heidelberg 2004.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共185页 << < 158 159 160 161 162 163 164 165 166 167 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：