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检索条件"任意字段=25th International Conference on Field Programmable Logic and Applications"

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On computing maximum likelihood phylogeny using FPGA 14th

On computing maximum likelihood phylogeny using FPGA

引用

14th international conference on field programmable logic and applications, FPL 2004

作者： Mak, Terrence S. T. Lam, K.P. Department of Systems Engineering and Engineering Management The Chinese University of Hong Kong Hong Kong

ISBN: (纸本)3540229892

Phylogenetic tree (or phylogeny) is a meaningful tree representation for the evolutionary history of different organisms that it has been shown useful in drug discovery, virus identification and functional genomic study [1]. the objective of this project is to develop efficient FPGA implementations for phylogenetic tree reconstruction algorithms. By taking advantage of hardware high-performance, we explore the possibilities of parallelization and system optimization to provide high-speed acceleration for the phylogeny inference. the Maximum Likelihood approach for inferring the phylogeny from molecular data has received much attention [2]. Although the optimal ML phylogenetic tree search problem is classified as NP-hard and it is difficult to find the optimal solution, the GAML algorithm (based on Genetic Algorithm and Maximum Likelihood) has been shown to find a good near-optimal solution in reasonable time [3]. In [4], we have shown that using HW/SW (Hardware/ Software) codesign for GAML implementation can provide significant speed-up when compared with software-only implementation. Our HW/SW system has good potential for handling large scale problems in real applications. In [5], an enhanced version of FPGA design with parallel and pipelined implementation for the likelihood evaluation is proposed. It has been shown 100 times faster than the single-CPU solution for the ML tree evaluation. To reduce precision loss attributed to truncation error in the FPGA, we are developing a dynamic floating-point alike structure based on the fixed-point architecture. We have also studied the implementation of phylogenetic tree reconstruction algorithm in the embedded platform (i.e. VirtexII-Pro Platform FPGA). Significant improvement in data transmission rate between hardware and software and higher clock frequency of FPGA have been realized [6]. © Springer-Verlag Berlin Heidelberg 2004.

关键词： field programmable gate arrays (FPGA)

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Power analysis attacks against FPGA implementations of the DES

Power analysis attacks against FPGA implementations of the D...

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14th international conference on field programmable logic and applications, FPL 2004

作者： Standaert, François-Xavier Örs, Sıddıka Berna Quisquater, Jean-Jacques Preneel, Bart UCL Crypto Group Laboratoire de Microélectronique Université Catholique de Louvain Place du Levant 3 Louvain-La-NeuveB-1348 Belgium Katholieke Universiteit Leuven Dept.ESAT/SCD-COSIC Kasteelpark Arenberg 10 Leuven-HeverleeB-3001 Belgium

ISBN: (纸本)3540229892

Cryptosystem designers frequently assume that secret parameters will be manipulated in tamper resistant environments. However, physical implementations can be extremely difficult to control and may result in the unintended leakage of side-channel information. In power analysis attacks, it is assumed that the power consumption is correlated to the data that is being processed. An attacker may therefore recover secret information by simply monitoring the power consumption of a device. Several articles have investigated power attacks in the context of smart card implementations. While FPGAs are becoming increasingly popular for cryptographic applications, there are only a few articles that assess their vulnerability to physical attacks. In this article, we demonstrate the specific properties of FPGAs w.r.t. Differential Power Analysis (DPA). First we emphasize that the original attack by Kocher et al. and the improvements by Brier et al. do not apply directly to FPGAs because their physical behavior differs substantially from that of smart cards. then we generalize the DPA attack to FPGAs and provide strong evidence that FPGA implementations of the Data Encryption Standard (DES) are vulnerable to such attacks. © Springer-Verlag Berlin Heidelberg 2004.

关键词： field programmable gate arrays (FPGA)

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Controlling an electrical motion system by a load instruction decoding algorithm using FPGA

Controlling an electrical motion system by a load instructio...

引用

IEEE international conference on Electronics, Circuits and Systems (ICECS)

作者： S. Cooper A. Kuperman R. Rabinovici Department of Electrical and Computer Engineering Ben-Gurion University of the Negev Beersheba Israel

this paper presents a motion control system which employs a load decoder, capable of analyzing the load value and changes, applied to the motor's rotor, decoding them into an instruction set for the controller input. the system is implemented in a field programmable gate array (FPGA) device, which have recently become affordable for implementing complicated motion control algorithms. All motion control logic is implemented in hardware (no software at all) and executes functions by the dedicated hardware logic. In such a case execution time becomes inherently fast and deterministic. this complicates the design, compared to the rather simple solution in software on DSP but offers reduced control system price which is essential for mass production applications. Moreover it can be easily transformed into ASIC for further cost reduction.

关键词： Motion control Control systems Decoding field programmable gate arrays logic devices Hardware Rotors programmable logic arrays Digital signal processing Weight control

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Design of high speed arithmetic encoder [image coding applications]

Design of high speed arithmetic encoder [image coding applic...

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international conference on Solid-State and Integrated Circuit Technology

作者： Mei Kuizhi Zheng Nanning Yao Ji Liu Yuehu The Institute of Artificial Intelligence and Robotics Xi'an Jiaotong University Xi'an China

ISBN: (纸本)078038511X

Focusing on the problem of path waiting or path circulation that existed in updating of the context table and the renorme and byteout procedure in the realization of the conventional arithmetic encoder in JPEG2000, a 3-step pipeline architecture is used on an FPGA to get high speed encoding. A method of updating the CX table is proposed, and a circuit with short delay is also implemented to detect the left zeros of the A-register. Multiplexers are adopted to accelerate the random left shift operation, and parallel processing based on data dependency is used to optimize the RTL code to shorten the main critical path. Finally, the updating of the logic of the context table is fully discussed. Experimental result show the encoder can work up to 107 MHz on Altera's EP1S25B672C7 and the critical path is 4.6 ns when synthesized in synopsys DC by the TSMC 0.25 /spl mu/m library.

关键词： Arithmetic Image coding Pipelines field programmable gate arrays Encoding Circuits Delay Multiplexing Acceleration Parallel processing

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Adding limited reconfigurability to superscalar processors 04

Adding limited reconfigurability to superscalar processors

引用

international conference on Parallel Architecture and Compilation Techniques (PACT)

作者： M. Epalza P. Ienne D. Mlynek Signal Processing Institute Switzerland Processor Architecture Laboratory Switzerland Swiss Federal Institute of Technology Lausanne Switzerland

ISBN: (纸本)9780769522296

When adding reconfigurability to custom hardware, one must take great care that the reduction in speed due to the reconfigurable logic should not cancel out the gains obtained by reconfiguration. these gains are greatest in very specific and computation-intensive applications, and lessen as the applications become more general and heterogeneous. In the case of superscalar processors, this leads to limiting the amount of reconfigurability to precise changes in existing functional units instead of adding a fully configurable functional unit. We present a detailed study of the modifications necessary in a superscalar processor to allow an FPU to be dynamically reconfigured as several ALUs with a minimal increase in the latency of these functional units. the timing of the FPU's multiplier tree and the decision about reconfiguration are exposed. As there is more than one simple unit involved, this decision is more global than a cycle-by-cycle reconfiguration and must be made for a longer period of time. We discuss possible policies for the dynamic reconfiguration decisions. the results show interesting gains of up to 56% in the best cases, and average gains of 10%, on typical architectures over a wide range of applications.

关键词： Reconfigurable logic field programmable gate arrays Hardware Signal processing Delay Automatic control Switches Computer applications Limiting Timing

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Simulation of an ingenious digital controller for a 6/4 pole switched reluctance motor

Simulation of an ingenious digital controller for a 6/4 pole...

引用

international conference on Power Electronics and Motion Control (IPEMC)

作者： S. Vijayan V. Ramprasath S. Paramasivam R. Arumugam Department of Electrical and Electronics Engineering Anna university Chennai Tamilnadu India

this paper discusses the process of designing a digital controller for a 6/4 switched reluctance motor (SRM) using VHDL. SRM is gaining importance nowadays as the high RPM of the motor plays a vital role in applications such as hard disk drive motors where high speed is necessary. Designing a controller for such a motor needs the aid of a processor, which has flexibilities in design and high speed in operation. FPGA provides the solution for the above requirement, as it is compact in size and micro programmed in logic. VHDL is very high-speed integrated circuits hardware descriptive language and is used for defining the functionalities of different modules of the controller. By implementing the controller in FPGA, PWM waveforms can be generated from the kit, which is used to drive the gate of the converter circuit. Most of the controllers, which are in use, occupy lot of space and consume a considerable amount of energy. the digital controller presented here has all its algorithms packed in a single chip, which makes the design easy. In this paper both sensor based and indirect control techniques are discussed.

关键词： Digital control Reluctance motors Reluctance machines field programmable gate arrays Process design Hard disks logic High speed integrated circuits Hardware Pulse width modulation

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13th international conference on field-programmable logic and applications, FPL 2003

13th International Conference on Field-Programmable Logic an...

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13th international conference on field-programmable logic and applications, FPL 2003

ISBN: (纸本)3540408223

the proceedings contain 146 papers. the special focus in this conference is on Communications applications, High Level Design Tools, Reconfigurable Architectures, Cryptographic applications, Place and Route Tools. the topics include: Reconfigurable circuits using hybrid hall effect devices;symbol timing synchronization in FPGA-based software radios;an architecture with tightly coupled VLIW processor and coarse-grained reconfigurable matrix;inter-processor connection reconfiguration based on dynamic look-ahead control of multiple crossbar switches;FPGA implementations of the RC6 block cipher;orchestrating routing structures to maximize routability;virtualizing hardware with multi-context reconfigurable arrays;a dynamically adaptive switching fabric on a multicontext reconfigurable device;reducing the configuration loading time of a coarse grain multicontext reconfigurable device;design strategies and modified descriptions to optimize cipher FPGA implementations;using partial reconfiguration in cryptographic applications;an implementation comparison of an IDEA encryption cryptosystem on two general-purpose reconfigurable computers;low power coarse-grained reconfigurable instruction set processor;encoded-low swing technique for ultra low power interconnect;building run-time reconfigurable systems from tiles;exploiting redundancy to speedup reconfiguration of an FPGA;efficient modular-pipelined AES implementation in counter mode on ALTERA FPGA;an FPGA-based performance analysis of the unrolling, tiling, and pipelining of the AES algorithm;branch optimisation techniques for hardware compilation;a model for hardware realization of kernel loops;globally asynchronous locally synchronous FPGA architectures and synthesizing on a reconfigurable chip an autonomous robot image processing system.

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Cyclone™:: A low-cost, high-performance FPGA

Cyclone™:: A low-cost, high-performance FPGA

引用

25th Annual Custom Integrated Circuits conference

作者： Leventis, P Chan, M Chan, M Lewis, D Nouban, B Powell, G Vest, B Wong, M Xia, RX Costello, J Altera Corp San Jose CA 95134 USA

ISBN: (纸本)0780378423

this paper describes the Altera Cyclone(TM) FPGA, an architecture specifically designed for low-cost, high-volume applications. An optimized routing architecture, simplified I/O structure, and carefully selected features combine to yield a 57% die size reduction relative to a Stratix(TM) device of similar logic density, with a 7% reduction in performance.

关键词： field programmable gate arrays

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Leakage power analysis of a 90nm FPGA

Leakage power analysis of a 90nm FPGA

引用

25th Annual Custom Integrated Circuits conference

作者： Tuan, T Lai, B Xilinx Res Labs San Jose CA 95134 USA

ISBN: (纸本)0780378423

Reconfigurable architectures, including FPGAs, are promising solutions for managing increasing design complexity while achieving both performance and flexibility. To support reconfiguration, FPGAs use more transistors per function than fixed-logic solutions, resulting in higher leakage power consumption. Consequently, FPGAs are generally not found in mobile applications. In this work, we analyze the leakage power of a low-cost, 90nm FPGA using detailed device-level simulations. the simulation methodology accounts for design-dependent variations and provides detailed leakage power breakdowns. the analysis quantifies the leakage power challenge in FPGAs, and identifies promising approaches for FPGA leakage power reduction.

关键词： field programmable gate arrays

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Improving DSP performance with a small amount of field programmable logic

Improving DSP performance with a small amount of field progr...

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13th international conference on field-programmable logic and applications (FPL 2003)

作者： Oliver, J Akella, V Univ Calif Davis Dept Elect & Comp Engn Davis CA 95616 USA

ISBN: (纸本)3540408223

We show a systematic methodology to create DSP + field-programmable logic hybrid architectures by viewing it as a hardware/software codesign problem. this enables an embedded processor architect to evaluate the trade-offs in the increase in die area due to the field programmable logic and the resultant improvement in performance or code size. We demonstrate our methodology with the implementation of a Viterbi decoder. A key result of the paper is that the addition of a field-programmable data alignment unit (FPDAU) between the register-file and the computational blocks provides 15%-22% improvement in the performance of a Viterbi decoder on the state-of-the-art TigerSHARC DSP. the area overhead of the FPDAU is small relative to the DSP die size and does not require any changes to the programming model or the instruction set architecture.

关键词： Economic and social effects

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