作者：
Ma, XJTong, JRFudan Univ
Microelect Dept ASIC & Syst State Key Lab Shanghai 200433 Peoples R China
FPGA is widely applied in datapathapplications, so it's all important design issue to contrive FPGA architecture fit for datapath circuit implementation. In this paper, we described a new FPGA architecture -- FDE...
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ISBN:
(纸本)078037889X
FPGA is widely applied in datapathapplications, so it's all important design issue to contrive FPGA architecture fit for datapath circuit implementation. In this paper, we described a new FPGA architecture -- FDEGA (field-programmable Datapath Enhanced Gate Array). the LC of FDEGA is optimized for datapath implementation. and can be programmed as either combinational or sequential device. FDEGA has hierarchical interconnection architecture. A chip with 16*16 LC array has been fabricated, and the design of LC and interconnection has been tested, and circuit sample chosen from practical digital system design has been implemented in FDEGA. the result proves that our design of FDEGA is correct.
this Paper deals withthe computation of some elementary functions using piecewise Minimax approximation and small tables. the strength of the method is that the same scheme is used to compute all the elementary funct...
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ISBN:
(纸本)9770520101
this Paper deals withthe computation of some elementary functions using piecewise Minimax approximation and small tables. the strength of the method is that the same scheme is used to compute all the elementary functions with similar delay and accuracy of lulp (unit in last place). the hardware implementation of this method requires one multiplier and one adder chosen among those available in the Virtex-II FPGA as they present the highest performances concerning. the delay and the area. the method has been implemented in a recursive structure which operates at a frequency of over than 25 Mhz.
the aim of a Rapid Prototyping System for electronic circuit design is to obtain a physical model as similar as possible to the final system as the hosting technology can allow. Large digital, integrated circuits are ...
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ISBN:
(纸本)3540408223
the aim of a Rapid Prototyping System for electronic circuit design is to obtain a physical model as similar as possible to the final system as the hosting technology can allow. Large digital, integrated circuits are substituted by complex and advanced fieldprogrammable Gate Arrays (FPGA's) which emulate the whole circuit functionality. these devices can provide more information than the pure circuit emulation itself, they provide a special scheme to access the device configuration and execution time information of the design state registers. this paper describes the UNSHADES-1 system and is focused on the set of software tools that provide easy management and access to this execution time information.
this paper presents the design and implementation of a novel architecture for FIR filters on Xilinx Virtex FPGAs. the architecture is particularly useful for handling the problem of signal boundaries filtering, which ...
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ISBN:
(纸本)3540408223
this paper presents the design and implementation of a novel architecture for FIR filters on Xilinx Virtex FPGAs. the architecture is particularly useful for handling the problem of signal boundaries filtering, which occurs in finite length signal processing (e.g. image processing). It cleverly exploits the Shift Register logic (SRL) component of the Virtex family in order to implement the necessary complex data scheduling, leading to considerable area savings compared to the conventional implementation (based on a hard router), with no speed penalty. Our architecture uses bit parallel arithmetic and is fully scalable and parameterisable. A case study based on the implementation of the standard low filter of the Daubechies-8 wavelet on Xilinx Virtex-E FPGAs is presented.
the paper is focused on rapid prototyping for FPGA using the high-level environment of MATLAB/Simulink. An approach using combination of the Xilinx System Generator (XSG) and Handel-C is reviewed. A design flow to min...
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ISBN:
(纸本)3540408223
the paper is focused on rapid prototyping for FPGA using the high-level environment of MATLAB/Simulink. An approach using combination of the Xilinx System Generator (XSG) and Handel-C is reviewed. A design flow to minimize HDL coding is considered.
In the research community wireless devices are fostering many design and development activities. the. augmented transmission bandwidth supplied by 3G transmission schemes will soon enable an ubiquitous fruition of mul...
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ISBN:
(纸本)3540408223
In the research community wireless devices are fostering many design and development activities. the. augmented transmission bandwidth supplied by 3G transmission schemes will soon enable an ubiquitous fruition of multimedia content. this paper proposes a reconfigurable, power-scalable architecture for hybrid video coding, suitable for the mobile environment. the complete FPGA design flow shows very interesting performances both in terms of throughput, and power consumption.
New non-HDL programming models for signal processing in FPGAs have focused primarily on building high-performance data paths. Along withthe ability to construct sophisticated custom signal processors comes increased ...
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ISBN:
(纸本)3540408223
New non-HDL programming models for signal processing in FPGAs have focused primarily on building high-performance data paths. Along withthe ability to construct sophisticated custom signal processors comes increased requirements for creating complex control circuitry. Recent enhancements to System Generator for DSP begin to address this need by providing mechanisms that include co-simulation interfaces to extend Simulink with HDL semantics, automatic compilation from Matlab m-code into Simulink and VHDL, and embedded microcontrollers. In this paper, we describe how such mechanisms can be used in a QAM receiver designed for a CCSDS standard.
Verification of large VLSI digital circuits is primarily accomplished through simulation. In general, there is a trade-off between speed of processing and accuracy. Software simulation tools can be very accurate but a...
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ISBN:
(纸本)3540408223
Verification of large VLSI digital circuits is primarily accomplished through simulation. In general, there is a trade-off between speed of processing and accuracy. Software simulation tools can be very accurate but are very slow compared to logic accelerators and emulation systems. these latter systems, many FPGA based, while two to three orders of magnitude faster than software, deliver inferior timing analysis, in the latter case and cycle-based simulation it is merely equivalent to functional simulation. APPLES (Associative Parallel Processor for logic Event-driven Simulation) is the first Full Gate-timing logic Hardware Simulator;implemented in Xilink Virtex-II technology. APPLES is a true simulator, delivering timing analysis withthe accuracy of a software simulator, but has the distinction that processing is executed entirely in hardware devoid of any machine code. this has the potential to permit APPLES to be one to two orders of magnitude faster than equivalent software systems.
this paper describes an efficient methodology for testing dedicated clock lines in fieldprogrammable Gate Arrays (FPGAs). A H-tree based clocking architecture is proposed along with a test scheme. the H-tree architec...
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this paper describes how an FPGA based prototype environment aided the development of two multi-million gate ASICs: an IEEE 802.11 medium access controller and an IEEE 802.11a/b/g physical layer processor. Prototyping...
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ISBN:
(纸本)3540408223
this paper describes how an FPGA based prototype environment aided the development of two multi-million gate ASICs: an IEEE 802.11 medium access controller and an IEEE 802.11a/b/g physical layer processor. Prototyping the ASICs on a reconfigurable platform enabled concurrent development by the hardware and software teams, and provided a high degree of confidence in the designs. the capabilities of modern FPGAs and their development tools allowed us to easily and quickly retarget the complex ASICs into FPGAs, enabling'-us to integrate the prototyping effort into our design flow from the start of the project. the effect was to accelerate the development cycle and generate an ASIC which had been through one pass of beta testing before tape-out.
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