Conventional protective devices as light curtains allow safe but often inconvenient flow of work. Unfortunately uncomfortable safety devices axe often bypassed or simply switched off. Consequently, the design of a vid...
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ISBN:
(纸本)3540408223
Conventional protective devices as light curtains allow safe but often inconvenient flow of work. Unfortunately uncomfortable safety devices axe often bypassed or simply switched off. Consequently, the design of a video based protective device, which avoids inconvenient processing steps is of special interest. the present paper describes favorable combinations of FPGA-hardware and algorithms, which allow safeguarding of work places if several constraints are met. the methods were originally developed for surveillance of press brakes, but it is easily adaptable to different types of machines or work places.
the use of FPGAs for cryptographic applications is highly attractive for a variety of reasons but at the same time there are many open issues related to the general security of FPGAs. this contribution attempts to pro...
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ISBN:
(纸本)3540408223
the use of FPGAs for cryptographic applications is highly attractive for a variety of reasons but at the same time there are many open issues related to the general security of FPGAs. this contribution attempts to provide a state-of-the-art description of this topic. First, the advantages of reconfigurable hardware for cryptographic applications are listed. Second, potential security problems of FPGAs are described in detail, followed by a proposal of a some countermeasure. third, a list of open research problems is provided. Even though there have been many contributions dealing withthe algorithmic aspects of cryptographic schemes implemented on FPGAs, this contribution appears to be the first comprehensive treatment of system and security aspects.
the design of a routing channel for an FPGA is a complex process requiring a careful balance of flexibility with silicon efficiency. With a growing move towards embedding FPGAs into SoC designs, and the new opportunit...
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ISBN:
(纸本)3540408223
the design of a routing channel for an FPGA is a complex process requiring a careful balance of flexibility with silicon efficiency. With a growing move towards embedding FPGAs into SoC designs, and the new opportunity to automatically generate FPGA architectures, this problem is even more critical. the design of a routing channel requires determining the number of routing tracks, the length of the wires in those tracks, and the positioning of the breaks between wires on the tracks. this paper focuses on the last problem, the placement of breaks in tracks to maximize overall flexibility. Our optimal algorithm for track placement finds a best solution provided the problem meets a number of restrictions. Our relaxed. algorithm is without restrictions, and finds solutions on average within 1.13% of optimal.
Elliptic Curve Public Key Cryptosystems are becoming increasingly popular for use in mobile devices and applications where bandwidth and chip area are limited. they provide much higher levels of security per key lengt...
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ISBN:
(纸本)3540408223
Elliptic Curve Public Key Cryptosystems are becoming increasingly popular for use in mobile devices and applications where bandwidth and chip area are limited. they provide much higher levels of security per key lengththan established public key systems such as RSA. the underlying operation of elliptic curve point multiplication requires modular multiplication, division/inversion and addition/subtraction. Division is by far the most costly operation in terms of speed. this paper proposes a new divider architecture and implementation on FPGA for use in an ECC processor.
Hardware packet-filters for firewalls, based on content-addressable memory (CAM), allow packet matching processes to keep in pace with network throughputs. However, the size of an FPGA chip may limit the size of a fir...
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ISBN:
(纸本)3540408223
Hardware packet-filters for firewalls, based on content-addressable memory (CAM), allow packet matching processes to keep in pace with network throughputs. However, the size of an FPGA chip may limit the size of a firewall rule set that can be implemented in hardware. We develop two irregular CAM structures for packet-filtering that employ resource sharing methods, with various trade-offs between size and speed. Experiments show that the use of these two structures are capable of reduction, up to 90%, of hardware resources without losing performance.
In October 2000 the National Institute of Standards and Technology chose Rijndael algorithm as the new Advanced Encryption Standard (AES). AES finds wide deployment in a huge variety of products making efficient imple...
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ISBN:
(纸本)3540408223
In October 2000 the National Institute of Standards and Technology chose Rijndael algorithm as the new Advanced Encryption Standard (AES). AES finds wide deployment in a huge variety of products making efficient implementations a significant priority. In this paper we address the design and the FPCA implementation of a fully key agile AES encryption core with 128-bit keys. We discuss the effectiveness of several design techniques, such as accurate floorplanning, the unrolling, tiling and pipelining transformations (also in the case of feedback modes of operation) to explore the design space. Using these techniques, four architectures with different level of parallelism, trading off area for performance, are described and their implementations on a Virtex-E FPGA part are presented. the proposed implementations of AES achieve better performance as compared to other blocks in the literature and commercial IP core on the same device.
the design of all-digital symbol timing synchronizers for FP,GAs is a complex task. there are several architectures available for VLSI wireless transceivers but porting them to a software defined radio (SDR) platform ...
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ISBN:
(纸本)3540408223
the design of all-digital symbol timing synchronizers for FP,GAs is a complex task. there are several architectures available for VLSI wireless transceivers but porting them to a software defined radio (SDR) platform is not straightforward. In this paper we report a receiver architecture prepared to support demanding protocols such as satellite digital video broadcast (DVB-S). In addition, we report hardware implementation and area utilization estimation. Finally we present implementation results of a DVB-S digital receiver on a Virtex-II Pro FPGA.
In this paper, we describe a compact stereo vision system which consists of one off-the-shelf FPGA board with one FPGA. this system supports (1) camera calibration for easy use and for simplifying the circuit, and (2)...
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ISBN:
(纸本)3540408223
In this paper, we describe a compact stereo vision system which consists of one off-the-shelf FPGA board with one FPGA. this system supports (1) camera calibration for easy use and for simplifying the circuit, and (2) left-right consistency check for reconstructing correct 3-D geometry from the images taken by the cameras. the performance of the system is limited by the calibration (which is, however, a must for practical use) because only one pixel data can be allowed to read in owing to the calibration. the performance is;however, 20 frame per second (when the size of images is 640 x 480, and 80 frames per second when the size of images is 320 x 240), which is fast enough for practical use such as vision systems for autonomous robots. this high performance can be realized by the recent progress of FPGAs and wide memory access to external RAMs (eight memory banks) on the FPGA board.
Distributed Arithmetic techniques are widely used to implement Sum-of-Products computations such as calculations found in multimedia applications like FIR filtering and Discrete Cosine Transform. this paper presents a...
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ISBN:
(纸本)3540408223
Distributed Arithmetic techniques are widely used to implement Sum-of-Products computations such as calculations found in multimedia applications like FIR filtering and Discrete Cosine Transform. this paper presents a flexible, low-power and high throughput array for implementing distributed arithmetic computations. Flexibility is achieved by using an array of elements arranged in an interconnect mesh similar to those employed in conventional FPGA architectures. We provide results which demonstrate a significant reduction in power consumption in addition to improvements in timing and area over standard FPGA architectures.
this paper presents a software tool to design intermediate frequency and baseband digital transceivers on FPGA. Main characteristic of this tool is that an ad-hoc interpolation or decimation filter chain composed by C...
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ISBN:
(纸本)3540408223
this paper presents a software tool to design intermediate frequency and baseband digital transceivers on FPGA. Main characteristic of this tool is that an ad-hoc interpolation or decimation filter chain composed by CIC, polyphase, pulse shaping, matched filters and a CORDIC-based or ROM-based mixer can be selected. the tool allows the software radio designer to develop downconverters and upconverters and, finally, automatically to generate the VHDL code to implement the system on Xilinx FPGAs.
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