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A functional spiking neuron hardware oriented model

A functional spiking neuron hardware oriented model

引用

7th international Work-conference on Artificial and Natural Neural Networks, IWANN 2003

作者： Upegui, Andres Peña-Reyes, Carlos Andrés Sanchez, Eduardo Swiss Federal Institute of Technology at Lausanne Logic Systems Laboratory Lausanne1015 Switzerland

ISBN: (纸本)3540402101

In this paper we present a functional model of spiking neuron intended for hardware implementation. the model allows the design of speed-and/or area-optimized architectures. Some features of biological spiking neurons are abstracted, while preserving the functionality of the network, in order to define an architecture easily implementable in hardware, mainly in field programmable gate arrays (FPGA). the model permits to optimize the architecture following area or speed criteria according to the application. In the same way, several parameters and features are optional, so as to allow more biologically plausible models by increasing the complexity and hardware requirements of the model. We present the results of three example applications performed to verify the computing capabilities of a simple instance of our model. © Springer-Verlag Berlin Heidelberg 2003.

关键词： field programmable gate arrays (FPGA)

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On-chip and off-chip real-time debugging for remotely-accessed embedded programmable systems

On-chip and off-chip real-time debugging for remotely-access...

引用

13th international conference on field-programmable logic and applications, FPL 2003

作者： Harkin, Jim Callaghan, Michael Peters, Chris McGinnity, thomas M. Maguire, Liam Intelligent Systems Engineering Laboratory University of Ulster Magee Campus Northland Rd BT48 7JL United Kingdom

ISBN: (纸本)3540408223

Embedded programmable systems are becoming common in system designs, resulting in the need for educational institutions to teach advanced embedded systems design and develop debugging competence in students. Remote laboratory experimentation provided as part of a web-based distance learning allows flexible access to on-campus resources free of time or geographical constraints. However, adapting and redeveloping existing software and hardware resources to this purpose is both time consuming and expensive. this paper introduces a remote-access laboratory architecture, which extends current e-learning strategies to provide real-time debugging for embedded programmable systems via the web. An example experiment illustrates the on-chip and off-chip real-time debugging capabilities of the laboratory. © Springer-Verlag Berlin Heidelberg 2003.

关键词： Embedded systems

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Using partial reconfiguration in cryptographic applications: An implementation of the IDEA algorithm

Using partial reconfiguration in cryptographic applications:...

引用

13th international conference on field-programmable logic and applications, FPL 2003

作者： Gonzalez, Ivan Lopez-Buedo, Sergio Gomez, Francisco J Martinez, Javier Escuela Politecnica Superior Universidad Autonoma de Madrid Cantoblanco MadridE-28049 Spain

ISBN: (纸本)3540408223

this paper shows that partial reconfiguration can notably improve the area and throughput of symmetric cryptographic algorithms implemented in FPGAs. In most applications the keys are fixed during a cipher session, so that several blocks, like module adders or multipliers, can be substituted for their constant-operand equivalents. these counterparts not only are faster, but also use significantly less resources. In this approach, the changes in the key are performed through a partial reconfiguration that modifies the constants. the international Data Encryption Algorithm (IDEA) has been selected as a case-study, and JBits has been chosen as the tool for performing the partial reconfiguration. the implementation occupies an 87% of a Virtex XCV600 and achieves a throughput of 8.3 GBits/sec. © Springer-Verlag Berlin Heidelberg 2003.

关键词： Computers

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A study on the design of floating-point functions in FPGAS

A study on the design of floating-point functions in FPGAS

引用

13th international conference on field-programmable logic and applications, FPL 2003

作者： Ortiz, Fernando E. Humphrey, John R. Durbano, James P. Prather, Dennis W. University of Delaware 140 Evans Hall NewarkDE19716 United States EM Photonics Inc 102 East Main St NewarkDE19711 United States

ISBN: (纸本)3540408223

Floating-Point Operations represent a common task in a variety of applications, but such operations often result in a bottleneck, due to the large number of machine cycles required to compute them. Even though the FPGA community has developed advanced algorithms to improve the speed of FLOPs, floating-point transcendental functions are still underdeveloped. In this paper, we discuss some of the tradeoffs faced when implementing floating-point functions in FPGAs. these techniques, including lookup tables, and CORDIC algorithms, have been used in the past for the implementation of fixed-point analytic functions. this paper seeks to apply those methods to floating-point functions. the implementation results from different versions of a floatingpoint sine function are summarized in terms of speed, area, and accuracy to understand the effect of different architectural alternatives. © Springer-Verlag Berlin Heidelberg 2003.

关键词： field programmable gate arrays (FPGA)

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An extensible, system-on-programmable-chip, content-aware internet firewall

An extensible, system-on-programmable-chip, content-aware in...

引用

13th international conference on field-programmable logic and applications, FPL 2003

作者： Lockwood, John W Neely, Christopher Zuver, Christopher Moscola, James Dharmapurikar, Sarang Lim, David Applied Research Laboratory Washington University in Saint Louis 1 Brookings Drive Campus Box 1045 Saint LouisMO63130 United States

ISBN: (纸本)3540408223

An extensible firewall has been implemented that performs packet filtering, content scanning, and per-flow queuing of Internet packets at Gigabit/second rates. the firewall uses layered protocol wrappers to parse the content of Internet data. Packet payloads are scanned for keywords using parallel regular expression matching circuits. Packet headers are compared to rules specified in Ternary Content Addressable Memories (TCAMs). Per-flow queuing is performed to mitigate the effect of Denial of Service attacks. All packet processing operations were implemented with reconfigurable hardware and fit within a single Xilinx Virtex XCV2000E field programmable Gate Array (FPGA). the singlechip firewall has been used to filter Internet SPAM and to guard against several types of network intrusion. Additional features were implemented in extensible hardware modules deployed using run-time reconfiguration. © Springer-Verlag Berlin Heidelberg 2003.

关键词： Denial-of-service attack

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Performance and area modeling of complete FPGA designs in the presence of loop transformations

Performance and area modeling of complete FPGA designs in th...

引用

13th international conference on field-programmable logic and applications, FPL 2003

作者： Shesha Shayee, K.R. Park, Joonseok Diniz, Pedro C. University of Southern California Information Sciences Institute 4676 Admiralty Way Suite 1001 Marina del ReyCA90292 United States

ISBN: (纸本)3540408223

Selecting which program transformations to apply when mapping computations to FPGA-based architectures leads to prohibitively long design exploration cycles. An alternative is to develop fast, yet accurate, performance and area models to understand the impact and interaction of the transformations. In this paper we present a combined analytical performance and area modeling for complete FPGA designs in the presence of loop transformations. Our approach takes into account the impact of input/output memory bandwidth and memory interface resources, often the limiting factor in the effective implementation of these computations. Our preliminary results reveal that our modeling is very accurate allowing a compiler tool to quickly explore a very large design space resulting in the selection of a feasible high-performance design. © Springer-Verlag Berlin Heidelberg 2003.

关键词： field programmable gate arrays (FPGA)

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Data processing system with self-reconfigurable architecture, for low cost, low power applications

Data processing system with self-reconfigurable architecture...

引用

13th international conference on field-programmable logic and applications, FPL 2003

作者： Lorenz, Michael G Mengibar, Luis Entrena, Luis Sánchez-Reillo, Raul Electronic Technology Department Universidad Carlos III de Madrid Spain

ISBN: (纸本)3540408223

In this paper, a low cost self-reconfigurable data processing system with a USB interface is presented. A single FPGA performs all processing and controls the multiple configurations without any additional elements, such as microprocessor, host computer or additional FPGAs. this architecture allows high performances at very low power consumption. In addition, a hierarchical reconfiguration system is used to support a large number of different processing tasks without the penalty in power consumption of a big local configuration memory. Due to its simplicity and low power, this data processing system is specially suitable for portable applications. © Springer-Verlag Berlin Heidelberg 2003.

关键词： Reconfigurable architectures

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Time and energy efficient matrix factorization using FPGAs

Time and energy efficient matrix factorization using FPGAs

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13th international conference on field-programmable logic and applications, FPL 2003

作者： Choi, Seonil Prasanna, Viktor K. Electrical Engineering-Systems University of Southern California Los Angeles United States

ISBN: (纸本)3540408223

In this paper, new algorithms and architectures for matrix factorization are presented. Two fully-parallel and block-based designs for LU decomposition on configurable devices are proposed. A linear array architecture is employed to minimize the usage of long interconnects, leading to lower energy dissipation. the designs are made scalable by using a fixed I/O bandwidth independent of the problem size. High level models for energy profiling are built and the energy performance of many possible designs is predicted. through the analysis of design tradeoffs, the block size that minimizes the total energy dissipation is identified. A set of candidate designs was implemented on the Xilinx Virtex-II to verify the estimates. Also, the performance of our designs is compared with that of state-of-the-art DSP based designs and with the performance of designs obtained using a state-of-the-art commercial compilation tool such as Celoxica DK1. Our designs on the FPGAs are significantly more time and energy efficient in both cases. © Springer-Verlag Berlin Heidelberg 2003.

关键词： field programmable gate arrays (FPGA)

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Modified fuzzy C-means clustering algorithm for real-time applications

Modified fuzzy C-means clustering algorithm for real-time ap...

引用

13th international conference on field-programmable logic and applications, FPL 2003

作者： Lázaro, Jesús Arias, Jagoba Martín, José L. Cuadrado, Carlos Escuela Superior de Ingenieros University of the Basque Country Alameda Urquijo s/n Bilbao48013 Spain

ISBN: (纸本)3540408223

the fuzzy approach in image processing is taking each day greater importance. It is greatly due to the fact that every new application of artificial vision is closer to human vision. this means that tightly knot algorithms are not always a good solution and a more "imprecise" and fuzzy approach is desirable. this paper describes a modified Fuzzy C-Means algorithm intended to be implemented in hardware. the original algorithm was modified to match the desired level of parallelism, speed and to simplify the hardware implementations. © Springer-Verlag Berlin Heidelberg 2003.

关键词： Image processing

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Efficient reconfigurable logic circuits for matching complex network intrusion detection patterns

Efficient reconfigurable logic circuits for matching complex...

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13th international conference on field-programmable logic and applications, FPL 2003

作者： Clark, Christopher R. Schimmel, David E. School of Electrical and Computer Engineering Georgia Institute of Technology AtlantaGA30332 United States

ISBN: (纸本)3540408223

this paper presents techniques for designing pattern matching circuits for complex regular expressions, such as those found in network intrusion detection patterns. We have developed a pattern-matching coprocessor that supports all the pattern matching functions of the Snort rule language [3]. In order to achieve maximum pattern capacity and throughput, the design focuses on minimizing circuit area while maintaining high clock speed. Using our approach, we are able to store the entire current Snort rule database consisting of over 1,500 rules and 17,000 characters into a single one-million- gate FPGA while comparing all patterns against traffic at gigabit rates. © Springer-Verlag Berlin Heidelberg 2003.

关键词： Pattern matching

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