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Power quality analysis of three stage fifteen level cascaded multilevel inverter by using FPGA controller for EV application

Power quality analysis of three stage fifteen level cascaded...

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IEEE Power India conference

作者： K. Sakthivel S. Albert Alexander School of Electrical Engineering Vellore Institute of Technology Vellore

ISBN: (数字)9798350367065

ISBN: (纸本)9798350367072

Sustainable power generation is characterized by zero carbon emissions in specific circumstances. However, this is primarily owing to their inherent generating mode, which involves the use of direct current (DC) power, as seen in solar photovoltaic (PV) systems, fuel cells, and other similar technologies. It is intended to encourage inverters to provide electricity to alternate current (AC) loads. Ensuring power quality is crucial while performing DC/AC inversion and is also vital for major electric vehicle (EV) applications, such as powering the EV motor. the required inverters can be the typical three-stage fifteen-level cascaded multilevel inverter. Enhancing the reliability of renewable energy sources can be achieved by employing EV motors and developing a 3-stage, 15-level inverter. this approach improves performance by lowering the number of switches and minimizing total harmonic distortion (thD). the utilization of pulse width modulation technology, in conjunction with an Artificial Neural Network (ANN) algorithm, results in a reduction in the number of switches and facilitates the identification of faults through diagnostic processes. the recommended controller employs an Artificial Neural Network (ANN) and field programmable Gate Array (FPGA) to precisely categorize errors in the proposed Multi-Level Inverter (MLI). In addition, the Total Harmonic Distortion (thD) is evaluated for various load conditions. the datasets are acquired by MATLAB simulation. the datasets are used for training and testing to identify the most optimal Artificial Neural Network (ANN) technique.

关键词： Total harmonic distortion Power quality Artificial neural networks Backpropagation algorithms logic gates Multilevel inverters Motors Electric vehicles Voltage control field programmable gate arrays

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Resource-Efficient 64-Bit Karatsuba Multiplier using LUTs and DSP Slices

Resource-Efficient 64-Bit Karatsuba Multiplier using LUTs an...

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international conference on Computer applications and Industrial Electronics (ICCAIE)

作者： Shakirah Hashim Nur Farraliza Mansor School of Computing Sciences College of Computing Informatics and Mathematics Universiti Teknologi MARA Shah Alam Malaysia

ISBN: (数字)9798350348798

ISBN: (纸本)9798350348804

Modern field programmable Gate Array (FPGA) is now equipped with Digital Signal Processing (DSP) block for faster computation. this feature can be exploited to speed-up the multiplication process which is widely needed during encryption. However, the operand size of DSP multipliers are asymmetric, 24 x 17 bits, thus complicates the multiplication process. As DSP has high-throughput function, it must be optimally used to avoid resource waste. thus, 64-bit Karatsuba multiplier is proposed in this paper to exploit the DSP advancement, based on two optimizations: operand decomposition and operand arrangement. Both optimizations are tailored to the DSP asymmetric multiplier architecture. the proposed design is implemented on Kintex 7. We only utilized 8 DSP slices and several slices of LUTs resource, smaller than non-standard tiling Karatsuba. In fact, we achieved higher DSP efficiency (97.6%) as each DSP slice is optimally utilized.

关键词： Industrial electronics Array signal processing Digital signal processing Computer architecture logic gates Table lookup Encryption

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Simulation and analysis of 1024 point FFT using Axi-protocol and Xilinx IP core

Simulation and analysis of 1024 point FFT using Axi-protocol...

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international conference on Applied Electromagnetics, Signal Processing and Communication (AESPC)

作者： A. Supraja Reddy B Khaleelu Rehman P. Anuradha Mohammed Abdul Nasar Mohd Ziauddin Jahnagir P. Chandra Sekhar Department of ECE Chaitanya Bharathi Institute of Technology Hyderabad Telangana India Department of Electrical Engineering University of Technology & Applied Sciences Nizwa Sultanate of Oman

ISBN: (数字)9798331528171

ISBN: (纸本)9798331528188

this paper focuses on the implementation of a 1024-point FFT. A 1024-point FFT is significant in various applications, including signal processing, image processing, and communications, where it is essential to handle large data sets efficiently. the primary objective of this paper is to design and implement a 1024-point Fast Fourier Transform (FFT) algorithm using Verilog. this implementation aims to efficiently compute the discrete Fourier transform of a signal in a hardware environment. To design and implement the Fast Fourier Transform in Verilog module using Xilinx Vivado and to Verify the Fast Fourier Transform through MATLAB. Designing of basic 4-point and 8-point FFT in Xilinx Vivado using Verilog HDL Code and verifying the model through MATLAB by comparing. Design of 1024-point FFT in Xilinx Vivado using Verilog HDL program and verify the model through *** Synthesis of the design is carried out using Zynq-Zedboard (XC7Z020)

关键词： Fast Fourier transforms Signal processing algorithms Mathematical models Real-time systems logic Hardware design languages MATLAB Low latency communication field programmable gate arrays Pipeline processing

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A High-speed Scanning Module Based on a DBR Tunable Laser for FBG Sensor Systems

A High-speed Scanning Module Based on a DBR Tunable Laser fo...

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international conference on Transparent Optical Networks

作者： Wenqian Yuan Kun Shang Chongqian Zhu Haikun Zhang Yanan Zhai Xingwei Sun Yaping Zhang University of Jinan Jinan Shandong China Shandong Institute of Industrial Technology Innovation Park Jinan Shandong China OptoChip Optoelectronics Ltd B120 Qilu Soft Park Jinan China

ISBN: (数字)9798350377323

ISBN: (纸本)9798350377330

As some physical parameter measurements (e.g. vibration) require a high-speed FBG demodulation system, a high-speed scanning module as the core part of this system is investigated. In this study, the design and implementation of a high-speed scanning module for Fiber Bragg Grating (FBG) sensing based on a Distributed Bragg Reflector (DBR) tunable laser and a field programmable Gate Array (FPGA) is presented. the innovatively designed and constructed high-speed FBG sensor system comprises a DBR laser, a laser drive circuit with self-programmed control algorithms, and a signal processing module. the overall performance of this high-speed FBG sensor system is evaluated and verified experimentally in terms of the validation of scanning rate, accuracy and stability. this high-speed FBG sensor system has opened a wide range of unique applications for the measurement of a variety of key physical parameters which require a high-speed FBG demodulation technique.

关键词： Vibrations Laser theory Measurement by laser beam logic gates Fiber gratings Sensor systems Distributed Bragg reflectors

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Enhancing a Soft GPU IP Reliability Against SEUs in Space: Modelling Approach and Criticality Analysis on a Radiation-Tolerant FPGA

Enhancing a Soft GPU IP Reliability Against SEUs in Space: M...

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international conference on System Reliability and Science (ICSRS)

作者： Matteo Monopoli Matteo Biondi Giovanni Todaro Pietro Nannipieri Silvia Moranti Cinzia Bernardeschi Luca Fanucci Department of Information Engineering University of Pisa Pisa Italy European Space Research and Technology Centre European Space Agency (ESA) Noordwijk The Netherlands IngeniArs S. r.l. Pisa Italy

ISBN: (数字)9798350354508

ISBN: (纸本)9798350354515

field programmable Gate Arrays find extensive use across various domains, ranging from telecommunications to Machine Learning tasks. In the context of space applications, they emerge as a highly favourable choice, owing to their high degree of flexibility and their accessibility in different silicon-grade technologies. However, due to the high associated costs of radiation-hardened devices, the prevalence of radiation-tolerant devices is more common in practical deployment scenarios. In this sense, robustness-enhancing techniques can still be applied, thus allowing the employment of these devices in long-duration tasks without the need for a radiation-hardened counterpart. In this paper, we propose a modelling approach for estimating the reliability of a digital design system in space before carrying out fault injection tests and radiation campaigns. For this purpose, we employ a high-level tool called Mobius to obtain a first reliability estimation against Single Event Upsets by means of Fault Tree Models. We also propose a novel methodology for defining which fault mitigation techniques should be applied to each design sub-module, considering the most commonly used in the space environment. In particular, we focus on a specific use case, namely a Soft Graphic Processing Unit IP, implemented on the Xilinx RT XQRKU060 FPGA. We analyze the criticality, power and area impact of the most important design parts of the GPU when implemented in hardware, introducing a classification approach for associating an appropriate fault mitigation technique with each of them. Finally, in the last section of the paper, we hint at future development and conclude the work.

关键词： Space vehicles Prevention and mitigation Graphics processing units Single event upsets logic gates Reliability engineering Hardware IP networks field programmable gate arrays Fault trees

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Information Metamaterials and Information Systems 46

Information Metamaterials and Information Systems

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46th international conference on Infrared, Millimeter and Terahertz Waves (IRMMW-thz)

作者： Cui, Tie Jun Southeast Univ Inst Electromagnet Space Nanjing 210096 Peoples R China Southeast Univ State Key Lab Millimeter Waves Nanjing 210096 Peoples R China

ISBN: (纸本)9781728194240

Metamaterials have great capabilities and flexibilities in controlling electromagnetic (EM) waves since their subwavelength meta-atoms can be designed and tailored in desired ways. However, once the structure-only metamaterials (i.e., passive metamaterials) are fabricated, their functions will be fixed. To control the EM waves dynamically, some active devices are integrated into the meta-atoms, yielding active metamaterials. Traditionally, the active metamaterials include tunable metamaterials and reconfigurable metamaterials, which have either small-range tunability or a few numbers of reconfigurability. Recently, a special kind of active metamaterials, digital coding and programmable metamaterials, have been presented, which can realize a large number of distinct functionalities and switch them in real time with the aid of field programmable gate array. More importantly, the digital coding representations of metamaterials make it possible to bridge the digital world and physical world using the metamaterial platform, and make the metamaterials process digital information directly, resulting in information metamaterials. In this regard, the information metamaterial is no longer an effective material or medium, but an information system. In this presentation, I will firstly introduce the evolution of metamaterials, and then present the concepts and basic principles of digital coding metamaterials and information metamaterials. With more details, I will introduce a series of information metamaterial systems, including the programmable meta-systems, software meta-systems, and intelligent meta-systems. Particularly, I will present two important applications of the information metamaterials: intelligent computational imaging and wireless communications.

关键词： Wireless communication Imaging Switches logic gates Metamaterials Encoding Software

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Design and Implementation on FPGA of a Real-Time Secure Audio Communication System

Design and Implementation on FPGA of a Real-Time Secure Audi...

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international conference on Communications, Signal Processing, and their applications (ICCSPA)

作者： Abdenour Kifouche Mohamed Salah Azzaz Youcef Alloun Walid Merdaci Electronic and Digital Systems Laboratory Ecole Militaire Polytechnique Algiers Algeria

ISBN: (数字)9798350384819

ISBN: (纸本)9798350384826

In communication systems, data transmitted over networks must be protected against access by unauthorized parties. Indeed, existing audio systems are based on classical cryptographic algorithms. However, the reliability of some of these algorithms is no longer guaranteed, and others need significant resources with regard to memory, energy, and computation time, making them unsuitable for resource-constrained boards. To rise to these challenging issues, this paper develops a secure real-time audio communication architecture based on chaotic systems. this architecture is implemented on a Nexys FPGA board. the encryption scheme undergoes two consecutive stages of confusion and diffusion. Statistical results confirm the robustness of the proposed encryption scheme against many attacks based on the NIST test, key sensitivity, key size, information entropy, and statistical analysis. the implementation results include 21% of logic elements and 0.43 W of dynamic power to carry out the desired functions. the proposed scheme can reach a maximum frequency of 254.38 MHz. Compared to related work, this paper proposes a lightweight encryption system able to be implemented in different resource-constrained hardware boards. In addition, the proposed solution covers the entire life cycle of an audio communication system, including audio acquisition, filtering, encryption/decryption, and data sending/receiving over WiFi. these features guarantee the successful use of this solution in audio communications systems.

关键词： Sensitivity Protocols Chaotic communication Statistical analysis Signal processing Real-time systems Robustness Encryption field programmable gate arrays Wireless fidelity

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the Fault Tolerant Černý Finite State Machine: A Concept and VHDL Models 11

The Fault Tolerant Černý Finite State Machine: A Concept a...

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11th IEEE international conference on Intelligent Data Acquisition and Advanced Computing Systems: Technology and applications, IDAACS 2021

作者： Kharchenko, Vyacheslav Tyurin, Sergey Fesenko, Herman Goncharovskij, Oleg National Aerospace University Department of Computer Systems Networks and Cybersecurity Kharkiv Ukraine Perm National Research Polytechnic University Department of Automation and Telemechanic Perm Russia

ISBN: (纸本)9781665426053

there is a well-known problem named a Finite State Machine (FSM) synchronization in discrete mathematic or the road coloring problem in graph theory. In such area, Černý-Starke conjecture was solved by Trahtman in 2007. applications of the FSM (herein after in this paper referred to as the Černý FSM) for reliability, safety and dependability can be considered as a new important direction in various domains such as Internet of things and cyber physical systems, embedded electronics and quantum computing, cyber security and resilience etc. this paper discusses ways of the fault tolerant FSM development using Trahtman theorem. the authors investigate the binary Černý FSM with eight states, simulate logic circuit, and formulate problem of the reset paths conserving for some fault model. © 2021 IEEE.

关键词： field programmable gate arrays (FPGA)

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Designing 64-Bit LUT based FFT Structure for High-Speed DSP applications

Designing 64-Bit LUT based FFT Structure for High-Speed DSP ...

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international conference on Communication Systems and Network Technologies (CSNT)

作者： M. Bharathi G. Amrutha Sai B. Divya Sree K Bharadwaj Karthik B. Uday Kiran Naik Yasha Jyothi Shirur VTU & Electronics and Communication Engineering Mohan Babu University Tirupati Andhra Pradesh India Electronics and Communication Engineering Mohan Babu University Tirupati Andhra Pradesh India Electronics and Communication Engineering BNM Institute of Technology Bangalore India

Digital signal Processing (DSP) utilizes the efficient Fast Fourier Transform (FFT) Methodology that is used to alter, filter, and decode digital audio, video, and image data. FFT is used to design Electrical Circuits, to solve differential equations, to analyze signals and to process images. Distributed Arithmetic (DA) is a multiplier-less implementation technique that computes the inner dot product between two signals-fixed and varying by using shifters and adders. It takes the values in a bit-serial fashion which suits for real-time processing. the Computation logic Blocks (CLBs) of field programmable Gate Anays (FPGAs) Utilize Distributed Arithmetic. FFT can be calculated using the DA method. the existing method to calculate FFT is based on complex multiplications and additions which consume time as well as power. Hence DA based FFT has been proposed in which the delay is 29.3% less and the power is 21.8% less than that of the existing method.

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Energy-Efficient Stochastic Computing Architectures for Neural Network Performance in FPGA Systems

Energy-Efficient Stochastic Computing Architectures for Neur...

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Mobile Computing and Sustainable Informatics (ICMCSI), international conference on

作者： A.Dinesh Babu C. Gomathy Department of Electronics and Communication Engineering Faculty of Engineering and Technology SRM Institute of Science and Technology Chennai India

ISBN: (数字)9798331522667

ISBN: (纸本)9798331522674

this paper presents an energy-efficient stochastic computing (SC) architecture tailored for neural network applications on FPGA platforms. the proposed architecture integrates a Bayesian neural network (BNN) computation unit with a novel hybrid stochastic number generator (SNG) that combines Linear Feedback Shift Registers (LFSRs) and Halton sequences. this hybrid approach enhances the quality of generated bit-streams, significantly reducing correlation and improving the accuracy of SC-based computations. Stochastic computing allows complex arithmetic operations to be performed using simple logical gates, reducing hardware complexity and power consumption. Bayesian neural networks, due to their probabilistic framework, align well with the random nature of SC, allowing for resilient and efficient computations in resource-constrained environments. Experimental evaluations were conducted on an FPGA, measuring power consumption, computational accuracy, and resource utilization across varying bit-stream lengths. Results indicate that the proposed architecture achieves approximately 25% lower power consumption compared to conventional SC-based neural network implementations, with an improvement in mean squared error (MSE) accuracy. this energy efficiency and accuracy make the architecture particularly suitable for embedded systems, IoT devices, and other applications requiring low-power, high-performance neural network solutions. the proposed design offers a scalable solution for future neural network implementations in energy-constrained environments, contributing to advancements in sustainable hardware design.

关键词： Accuracy Power demand Neural networks Stochastic processes Computer architecture Energy efficiency Hybrid power systems Hardware Computational efficiency field programmable gate arrays

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