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检索条件"任意字段=25th International Conference on Field Programmable Logic and Applications"

共 1847 条记录，以下是1691-1700 订阅

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Fully parameterized discrete wavelet packet transform architecture oriented to FPGA

Fully parameterized discrete wavelet packet transform archit...

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13th international conference on field-programmable logic and applications, FPL 2003

作者： Payá, Guillermo Peiró, Marcos M. Ballester, Francisco Mora, Francisco Universidad Politécnica de Valencia Department of Electronic Engineering Camino de Vera s/n 46022 Spain

ISBN: (纸本)3540408223

the present paper describes a fully parameterized Discrete Wavelet Packet Transform (DWPT) architecture based on a folded Distributed Arithmetic implementation, which makes possible to design any kind of wavelet bases. the proposed parameterized architecture allows different CDF wavelet coefficient with variable bit precision (data input and output size, and coefficient length). Moreover, by combining different blocks in cascade, we can expand as many complete stages (wavelet packet levels) as we require. Our architecture need only two FIR filters to calculate various wavelet stages simultaneously, and specific VIRTEX family resources (SRL16E) have been instantiated to reduce area and increase frequency operation. Finally, a DWPT implementation for CDF(9,7) wavelet coefficients is synthesized on VIRTEX-II 3000-6 FPGA for different precisions. © Springer-Verlag Berlin Heidelberg 2003.

关键词： field programmable gate arrays (FPGA)

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An algorithm designer’s workbench for platform FPGAs

An algorithm designer’s workbench for platform FPGAs

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13th international conference on field-programmable logic and applications, FPL 2003

作者： Mohanty, Sumit Prasanna, Viktor K. Electrical Engineering Systems University of Southern California CA United States

ISBN: (纸本)3540408223

Growing gate density, availability of embedded multipliers and memory, and integration of traditional processors are some of the key advantages of Platform FPGAs. Such FPGAs are attractive for implementing compute intensive signal processing kernels used in wired as well as wireless mobile devices. However, algorithm design using Platform FPGAs, with energy dissipation as an additional performance metric for mobile devices, poses significant challenges. In this paper, we propose an algorithm designer’s workbench that addresses the above issues. the workbench supports formal modeling of the signal processing kernels, evaluation of latency, energy, and area of a design, and performance tradeoff analysis to facilitate optimization. the workbench includes a high-level estimator for rapid performance estimation and widely used low-level simulators for detailed simulation. Features include a confidence interval based technique for accurate power estimation and facility to store algorithm designs as library of models for reuse. We demonstrate the use of the workbench through design of matrix multiplication algorithm for Xilinx Virtex-II Pro. © Springer-Verlag Berlin Heidelberg 2003.

关键词： field programmable gate arrays (FPGA)

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Design strategies and modified descriptions to optimize cipher FPGA implementations: Fast and compact results for DES and triple-DES

Design strategies and modified descriptions to optimize ciph...

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13th international conference on field-programmable logic and applications, FPL 2003

作者： Rouvroy, Gaël Standaert, François-Xavier Quisquater, Jean-Jacques Legat, Jean-Didier UCL Crypto Group Laboratoire de Microélectronique Université catholique de Louvain Place du Levant 3 Louvain-La-NeuveB-1348 Belgium

ISBN: (纸本)3540408223

In this paper, we propose a new mathematical DES description that allows us to achieve optimized implementations in term of ratio throughput/Area. First, we get an unrolled DES implementation that works at data rates of 21.3 Gbps (333 MHz), using Virtex-II technology. In this design, the plaintext, the key and the mode (encryption/ decrytion) can be changed on a cycle-by-cycle basis with no dead cycles. In addition, we also propose sequential DES and triple-DES designs that are currently the most efficient ones in term of resources used as well as in term of throughput. Based on our DES and triple-DES results, we also set up conclusions for optimized FPGA design choices and possible improvement of cipher implementations with a modified structure description. © Springer-Verlag Berlin Heidelberg 2003.

关键词： field programmable gate arrays (FPGA)

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FPGA implementations of the RC6 block cipher

FPGA implementations of the RC6 block cipher

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13th international conference on field-programmable logic and applications, FPL 2003

作者： Beuchat, Jean-Luc Laboratoire de l’Informatique du Parallélisme Ecole Normale Supérieure de Lyon 46 Allée d’Italie Lyon Cedex 07F–69364 France

ISBN: (纸本)3540408223

RC6 is a symmetric-key algorithm which encrypts 128-bit plaintext blocks to 128-bit ciphertext blocks. the encryption process involves four operations: integer addition modulo 2w, bitwise exclusive or of two w-bit words, rotation to the left, and computation of f(X) = (X(2X + 1)) mod 2w, which is the critical arithmetic operation of this block cipher. In this paper, we investigate and compare four implementations of the f(X) operator on Virtex-E and Virtex-II devices. Our experiments show that the choice of an algorithm is strongly related to the target FPGA family. We also describe several architectures of a RC6 processor designed for feedback or non-feedback chaining modes. Our fastest implementation achieves a throughput of 15.2 Gb/s on a Xilinx XC2V3000-6 device. © Springer-Verlag Berlin Heidelberg 2003.

关键词： field programmable gate arrays (FPGA)

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A data acquisition reconfigurable coprocessor for virtual instrumentation applications

A data acquisition reconfigurable coprocessor for virtual in...

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13th international conference on field-programmable logic and applications, FPL 2003

作者： Dolores Valdés, M. Moure, María J. Quintáns, Camilo Mandado, Enrique Instituto de Electrónica Aplicada "Pedro Barrié de la Maza" Universidad de Vigo Spain Departamento de Tecnología Electrónica Universidad de Vigo Spain

ISBN: (纸本)3540408223

Virtual instruments intended for electronic circuits verification arose from the combination of computers supporting advanced graphical interfaces with data acquisition systems providing input/output capabilities. In order to increase the versatility and the operation rate of virtual instruments, we have designed several data acquisition/generation modules based on reconfigurable hardware. By this way, not only the software modules but also the hardware functions are dynamically changed according to the requirements of each specific instrument. the main basis of the software and hardware levels of reconfigurable virtual instruments are described in this paper. this methodology summarize our experience in the design of virtual instrumentation platforms oriented to different measurement applications. Finally, a new data acquisition/ generation coprocessor based on FPGAs and optimized for the implementation of portable instruments is described. © Springer-Verlag Berlin Heidelberg 2003.

关键词： Data acquisition

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Power analysis of FPGAs: How practical is the attack?

Power analysis of FPGAs: How practical is the attack?

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13th international conference on field-programmable logic and applications, FPL 2003

作者： Standaert, François-Xavier Van Oldeneel Tot Oldenzeel, Loïc Samyde, David Quisquater, Jean-Jacques UCL Crypto Group Laboratoire de Microélectronique Université Catholique de Louvain Place du Levant 3 Louvain-La-NeuveB-1348 Belgium

ISBN: (纸本)3540408223

Recent developments in information technologies made the secure transmission of digital data a critical design point. Large data flows have to be exchanged securely and involve encryption rates that sometimes may require hardware implementations. Reprogrammable devices such as field programmable Gate Arrays are highly attractive solutions for hardware implementations of encryption algorithms and several papers underline their growing performances and flexibility for any digital processing application. Although cryptosystem designers frequently assume that secret parameters will be manipulated in closed reliable computing environments, Kocher et al. stressed in 1998 that actual computers and microchips leak information correlated with the data handled. Side-channel attacks based on time, power and electromagnetic measurements were successfully applied to the smart card technology, but we have no knowledge of any attempt to implement them against FPGAs. this paper examines how monitoring power consumption signals might breach FPGA-security. We propose first experimental results against FPGA-implementations of cryptographic algorithms in order to confirm that power analysis has to be considered as a serious threat for FPGA security. We also highlight certain features of FPGAs that increase their resistance against side-channel attacks. © Springer-Verlag Berlin Heidelberg 2003.

关键词： field programmable gate arrays (FPGA)

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Video signal encoder and decoder creation ways research [digital TV applications]

Video signal encoder and decoder creation ways research [dig...

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international conference on CAD Systems in Microelectronics (CADSM)

作者： V. Hlukhov A. Melnyk V. Puyda ICTAM Lviv Polytechnic National University L'viv Ukraine

In this article are described a TV information encoder and decoder algorithm; along with its research and development principals. Also these principals realized in consumer electronics using modern micro controllers a... 详细信息

关键词： Decoding Encoding programmable logic arrays Teletext Cable TV Signal processing Consumer electronics programmable control Viterbi algorithm Reed-Solomon codes

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Case study of a functional genomics application for an FPGA-based coprocessor

Case study of a functional genomics application for an FPGA-...

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13th international conference on field-programmable logic and applications, FPL 2003

作者： Van Court, Tom Herbordt, Martin C. Barton, Richard J. Department of Electrical and Computer Engineering Boston University BostonMA02215 United States Department of Electrical and Computer Engineering University of Houston HoustonTX77204 United States

ISBN: (纸本)3540408223

Although microarrays are already having a tremendous impact on biomedical science, they still present great computational challenges. We examine a particular problem involving the computation of linear regressions on a large number of vector combinations in a high dimensional parameter space, a problem that was found to be virtually intractable on a PC cluster. We observe that characteristics of this problem map particularly well to FPGAs and confirm this with an implementation that results in a 1000-fold speed-up over a serial implementation. Other contributions involve the data routing structure, the analysis of bit-width allocation, and the handling of missing data. Since this problem is representative of many in functional genomics, part of the overall significance of this work is that it points to a potential new area of applicability for FPGA coprocessors. © Springer-Verlag Berlin Heidelberg 2003.

关键词： field programmable gate arrays (FPGA)

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Development of an industrial communication interface for a temperature sensor

Development of an industrial communication interface for a t...

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international conference on Emerging Technologies and Factory Automation (ETFA)

作者： M. Gonzalez-Romero M.A. Dominguez-Gomez M.D. Valdes-Pena Department of Electronic Technology University of Vigo Vigo Spain

fieldbuses are the most common used communication systems in industrial applications. Nowadays there are a lot of incompatible different solutions causing economic waste when little change in bus definitions are carried out. this paper proposes the implementation of reconfigurable fieldbuses using reconfigurable devices like FPGA (field programmable gate array) or PLD (programmable logic device). To evaluate the viability of this solution, this work implements the PROFIBUS (Process fieldbus) protocol in an Altera's FPGA to connect a temperature sensor to a PROFIBUS bus. the physical level of the protocol as well as the required services of the data link level have been implemented in the FPGA.

关键词： Communication industry Temperature sensors Communication system control Protocols field programmable gate arrays field buses Automatic control Data security programmable logic arrays Actuators

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FPGA implementation of radix 2 division with over-redundant quotient selection

FPGA implementation of radix 2 division with over-redundant ...

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international conference on Microelectronics, ICM

作者： A.A. Ibrahem H. Elsimary A.E. Salama Electronics Research Institute Cairo Egypt Cairo University Cairo Egypt

the flexibility of field programmable gate arrays (FPGAs) can provide arithmetic intensive applications with the benefites of custom hardware but without the high cost of custom silicon implementations. In this paper present the adaptation of radix 2 division algorithm for lookup table based FPGAs implementation. this division algorithm is well suited for IEEE 754 standard operands belonging to the range. the implementation has been done with xilinx technology and FPGA-Advantage CAD tools.

关键词： field programmable gate arrays logic Arithmetic Hardware Application software Costs Table lookup Silicon Circuits Fabrication

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