Reconfigurable logic is often integrated into a computer system as a combination of one CPU and one or more FPGAs. Here we investigated in the integration of FPGAs as coprocessors into a parallel computer system, resp...
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In this paper, we present a new placement method which provides short implementation times for today’s high capacity FPGAs within a direct mapping environment. We show that using additional component information is b...
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For data intensive applications like Digital Signal Processing, Image Processing, and Pattern Recognition, memory reads and writes constitute a large portion of the total design execution time. Withthe advent of on-c...
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this paper presents the full-duplex architecture of the X-MatchPRO lossless data compressor and its highly integrated implementation in a nonvolatile reprogrammable ProASIC FPGA. the X-MatchPRO architecture offers a d...
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Asynchronous logic design has been around for decades. However, only recently has it gained any commercial success. Research has focused on a wide variety of uses, from microprocessor design to low power circuits. the...
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this paper describes a structured technique for providing full observability and controllability for functionally debugging FPGA designs in hardware, capabilities which are currently not available otherwise. Similar i...
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this paper presents the benefits of using a generic FPGA tool set developed at the university of Brest for programming virtual FPGA. From a high level description of the FPGA architecture, the basic tools such a place...
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the proceedings contain 74 papers. the special focus in this conference is on Invited Keynote 1 and Architectural Frameworks. the topics include: Technology trends and adaptive computing;prototyping framework for reco...
ISBN:
(纸本)3540424997
the proceedings contain 74 papers. the special focus in this conference is on Invited Keynote 1 and Architectural Frameworks. the topics include: Technology trends and adaptive computing;prototyping framework for reconfigurable processors;an emulator for exploring RaPiD configurable computing architectures;a new placement method for direct mapping into LUT-based FPGAs;fGREP - fast generic routing demand estimation for placed FPGA circuits;macrocell architectures for product term embedded memory arrays;gigahertz reconfigurable computing using SiGe HBT BiCMOS FPGAs;memory synthesis for FPGA-based reconfigurable computers;implementing a hidden markov model speech recognition system in programmablelogic;implementation of (normalised ) RLS lattice on virtex;accelerating matrix product on reconfigurable hardware for signal processing;static profile-driven compilation for FPGAs;synthesizing RTL hardware from java byte codes;from behavioral specification to multi-FPGA-prototype;secure configuration of fieldprogrammable gate arrays;single-chip FPGA implementation of the advanced encryption standard algorithm;jbits™ implementations of the advanced encryption standard (rijndael );task-parallel programming of reconfigurable systems;chip-based reconfigurable task management;configuration caching and swapping;multiple stereo matching using an extended architecture;implementation of a NURBS to bézier conversor with constant latency;reconfigurable frame-grabber for real-time automated visual inspection (RT-AVI ) systems;processing models for the next generation network;tightly integrated placement and routing for FPGAs;a tool for the simultaneous placement and detailed routing of gate-arrays;reconfigurable router modules using network protocol wrappers;development of a design framework for platform-independent networked reconfiguration of software and hardware and the molen ρμ-coded processor.
the Rijndael algorithm has been selected as the new Advanced Encryption Standard. Several JBits implementations of this algorithm are described which target the Virtex™ FPGA family. As illustrated by sample code, JBit...
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this paper describes the successful implementation of a hardware demonstrator for real-time JPEG standard colour image compression and decompression at picture refresh rates up to 25 frames per second using an FPGA-ce...
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