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DReAM: A dynamically reconfigurable architecture for future mobile communication applications 10th

引用

10th international conference on field-programmable logic and applications, FPL 2000

作者： Becker, Jürgen Pionteck, thilo Glesne, Manfred Darmstadt University of Technology Institute of Microelectronic Systems Karlstr. 15 DarmstadtD-64283 Germany

ISBN: (纸本)3540678999

the development of current and future broadband access techniques into the wireless domain introduces new and flexible network architectures with difficult and interesting challenges, e. g. access mechanisms, energy conservation, error rate, transmission speed characteristics of the wireless links and mobility aspects. this paper discusses first the major challenges in hardware architecture design of reconfigurable system-on-a-chip solutions for the digital baseband processing in future mobile radio devices. the focus of the paper is the introduction of a new dynamically reconfigurable hardware architecture tailored to this application area. Its performance issues and potential are discussed by the implementation of a flexible and computationintensive component of future mobile terminals. © Springer-Verlag Berlin Heidelberg 2000.

关键词： Network architecture

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A threshold logic-based reconfigurable logic element with a new programming technology 10th

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10th international conference on field-programmable logic and applications, FPL 2000

作者： Aoyama, Kazuo Sawada, Hiroshi Nagoya, Akira Nakajima, Kazuo NTT Communication Science Laboratories 2-4 Hikaridai Seika-cho Soraku-gun Kyoto619-0237 Japan NTT Network Innovation Laboratories 1-1 Hikarinooka Yokosuka-Shi Kanagawa239-0847 Japan Department of Electrical and Computer Engineering University of Maryland College ParkMD20742 United States

ISBN: (纸本)3540678999

We introduce a new reconfigurable logic element. Its operations are based on threshold logic and it can store its own configuration data. the element is composed of threshold gates which are implemented in a two-level feed-forward neuron MOS circuit. We present a effective method of switching and storing the values of two variable thresholds in a neuron MOS transistor so as to reconfigure the element without requiring any additional memory circuit or device. Circuit simulation results are provided to verify the correct operations of the reconfigurable element in the following four function modes: symmetric function modes with/without configuration data storage, and multiplexer function modes with/without control data storage. © Springer-Verlag Berlin Heidelberg 2000.

关键词： Circuit simulation

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A comparison of FPGA implementations of bit-level and word-level matrix multipliers 10th

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10th international conference on field-programmable logic and applications, FPL 2000

作者： Grover, Radhika S. Shang, Weijia Li, Qiang Department of Computer Engineering Santa Clara University Santa ClaraCA United States

ISBN: (纸本)3540678999

We have implemented a novel bit-level matrix multiplier on a Xilinx FPGA chip where each processing element does a simple operation of adding three to six bits to generate one partial sum bit and one to two carryout bits. the speedup over word-level is possible because individual bits of a word do not have to be processed as a unit in a bit-level architecture. It is shown in a previous work that bit-level architectures for fixed point applications can be O(log p) times faster than the corresponding word-level architecture where p is the word length. In this paper we implemented the bit-level matrix multiplier on a Xilinx FPGA chip that is compared to a word-level matrix multiplier composed of highly optimized multiplier and adder macros available in the Xilinx Core generator library. the architecture presented in this paper is even faster than previous ones by breaking the critical path in the dependence graph into half. Our results show that speedup by a factor of 2 can be obtained in practice. © Springer-Verlag Berlin Heidelberg 2000.

关键词： field programmable gate arrays (FPGA)

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Static and dynamic reconfigurable designs for a 2D shape-adaptive DCT 10th

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10th international conference on field-programmable logic and applications, FPL 2000

作者： Gause, Jörn Cheung, Peter Y. K. Luk, Wayne Department of Electrical and Electronic Engineering Imperial College of Science Technology and Medicine LondonSW7 2BT United Kingdom Department of Computing Imperial College of Science Technology and Medicine LondonSW7 2AZ United Kingdom

ISBN: (纸本)3540678999

this paper presents two reconfigurable design approaches for a two dimensional Shape-Adaptive Discrete Cosine Transform (2D SA-DCT). the SA-DCT is an example of a new type of multimedia video processing algorithm where the computations performed are data dependent. A static design, where the configuration does not change during execution of the task, is presented. the use of a data dependence graph (DDG) is proposed which represents the computations and input signals required to calculate a particular output signal depending on a variable input parameter. By re-structuring the DDG and exploiting possible sharing of FPGA resources for different entities within the SA-DCT, it is demonstrated that the area required for an implementation can be significantly reduced. An alternative dynamic approach is also introduced where the FPGA’s configuration may change over time. this is well suited to using dynamically reconfigurable logic but suffers from long reconfiguration time if current FPGAs are used. © Springer-Verlag Berlin Heidelberg 2000.

关键词： field programmable gate arrays (FPGA)

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Performance penalty for fault tolerance in roving STARs 10th

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10th international conference on field-programmable logic and applications, FPL 2000

作者： Emmert, John M. Stroud, Charles E. Cheatham, Jason Taylor, Andrew M. Kataria, Pankaj Abramovici, Miron Dept of Electrical and Computer Engineering University of North Carolina at Charlotte United States Dept of Electrical Engineering University of Kentucky United States Bell Labs - Lucent Technologies Murray HillNJ United States

ISBN: (纸本)3540678999

In this paper we analyze the performance penalty of a fault-tolerant (FT) adaptive computing system (ACS) that implements the roving Self Testing AReas (STARs) approach for on-line testing and fault tolerance for FPGAs[1,5]. For most benchmarks, the presence of the STARs increases the critical path delay by 4.6% to 22%, and preallocating spare cells for fault tolerance causes an additional increase of up to 37%.We also present a procedure for estimating the worst case performance penalty caused by an incremental change of an already placed and routed FPGA. this estimate can be used to guide the selection of fault-tolerant reconfigurations to minimize their impact on the system timing. Our results show that the estimate is within 10% of the real delay values 1. © Springer-Verlag Berlin Heidelberg 2000.

关键词： field programmable gate arrays (FPGA)

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Task rearrangement on partially reconfigurable FPGAs with restricted buffer 10th

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10th international conference on field-programmable logic and applications, FPL 2000

作者： Elgindy, Hossam Middendorf, Martin Schmeck, Hartmut Schmidt, Bernd School of Computer Science and Engineering University of New South Wales Sydney2052 Australia Institute of Applied Computer Science and Formal Description Methods University of Karlsruhe KarlsruheD-76128 Germany

ISBN: (纸本)3540678999

Partially reconfigurable FPGAs can be shared among multiple independent tasks. When partial reconfiguration is possible at runtime the FPGA controller can decide on-line were to place new tasks on the FPGA. Since on–line allocation suffers from fragmentation, tasks can end up waiting despite there being sufficient, albeit non–contiguous resources available to service them. Rearranging a subset of the tasks executing on the FPGA often allows the next pending task to be processed sooner. In this paper we study the problem of placing and rearranging tasks that are supplied by input streams which have constant data rates. When such tasks are rearranged, the arriving input data have to be buffered while the execution is suspended. We describe and evaluate a genetic algorithm for identifying and scheduling feasible rearrangements when moving tasks are reloaded from off–chip and buffer size is limited. © Springer-Verlag Berlin Heidelberg 2000.

关键词： field programmable gate arrays (FPGA)

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Analysis of RNS-FPL synergy for high throughput DSP applications: Discrete wavelet transform 10th

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10th international conference on field-programmable logic and applications, FPL 2000

作者： Ramírez, Javier García, Antonio Fernández, Pedro G. Parrilla, Luis Lloris, Antonio Dept. of Electronics and Computer Technology Campus Universitario Fuentenueva Granada18071 Spain Dept. of Electrical Engineering Escuela Politécnica Superior Jaén23071 Spain

ISBN: (纸本)3540678999

this paper focuses on the implementation over FPL devices of high throughput DSP applications taking advantage of RNS arithmetic. the synergy between the RNS and modern FPGA device families, providing built-in tables and fast carry and cascade chains, makes it possible to accelerate MAC intensive real-time and DSP systems. In this way, a slow high dynamic range binary 2’s complement system can be partitioned into various parallel and high throughput small word-length RNS channels without inter-channel carry dependencies. To illustrate the design methodology, novel RNS-based architectures for multi-octave orthogonal DWT and its inverse are implemented using structural level VHDL synthesis. Area analysis and performance simulation are conducted. A relevant throughput improvement for the proposed RNS-based solution is obtained, compared to the equivalent 2’s complement implementation. © Springer-Verlag Berlin Heidelberg 2000.

关键词： Discrete wavelet transforms

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A placement algorithm for FPGA designs with multiple I/O standards 10th

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10th international conference on field-programmable logic and applications, FPL 2000

作者： Anderson, Jason Saunders, Jim Nag, Sudip Madabhushi, Chari Jayaraman, Rajeev Xilinx Inc. 2100 Logic Drive San JoseCA95124 United States

ISBN: (纸本)3540678999

State-of-the-art FPGAs possess I/O resources that can be configured to support a wide variety of I/O standards [1]. In such devices, the I/O resources are grouped into banks. One of the consequences of the banked organization is that all of the I/O objects that are placed within a bank must use „compatible"I/O standards. the compatibility of I/O standards is based on each standard’s supply and reference voltage requirements. For designs that use more than one I/O standard, the constraints associated with the banked organization lead to a constrained I/O pad placement problem. Meeting these constraints with a minimal deleterious effect on traditional objectives like minimizing wirelength turns out to be quite challenging. In this paper, we present a placement algorithm that operates in the context of these constraints. Our approach uses a combination of simulated annealing, weighted bipartite matching and constructive packing to produce a feasible I/O placement. Results show that the proposed algorithm produces placements with wirelength characteristics that are similar to the placements produced when pad placement is unconstrained. © Springer-Verlag Berlin Heidelberg 2000.

关键词： Simulated annealing

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the modular architecture of SYNthUP, FPGA based PCI board for real-time sound synthesis and digital signal processing

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10th international conference on field-programmable logic and applications, FPL 2000

作者： Raczinski, Jean-Michel Sladek, Stéphane CEMAMu France Télécom R and D B403 38-40 rue du Général Leclerc Issy-Les-Moulineaux Cedex 992794 France

ISBN: (纸本)3540678999

SYNthUP is a standard PCI plug-in board based on Xilinx FPGAs. It has been designed at CEMAMu for real-time sound synthesis and can be used for general purpose digital signal processing. Its modular architecture features a PCI interface, seven identical cells dedicated to computing, each made-up of one FPGA that drives two independent 4M×16 SDRAM with separate address and data buses. An array of five FPGAs is dedicated to data exchange between the cells and also drives five 12 bit ports. An eight cell is used for processing control, synthesis parameters update for example. PCI bus mastering (scattergather DMA) and a total of 128M bytes of dual port SDRAM allow the synthesizer to function independently of the host. the paper introduces our first results in additive synthesis and the implementation of adaptive FIR filters with distributed arithmetic. © Springer-Verlag Berlin Heidelberg 2000.

关键词： field programmable gate arrays (FPGA)

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Area-efficient implementation of a fast square root algorithm

Area-efficient implementation of a fast square root algorith...

引用

IEEE international Caracas conference on Devices, Circuits and Systems

作者： M.T. Tommiska Laboratory of Signal Processing and Computer Technology Helsinki University of Technology Finland

An area-efficient implementation of a fast-converging square-root algorithm is presented. the design of special arithmetic operations differs in many ways from the traditional tasks that digital designers are used to, and the role of parameterizability and mapping of mathematical algorithms onto digital hardware is discussed. Certain real-world applications requiring the use of the square-root operator are presented, and it is argued that implementing special arithmetic operations directly in hardware offers significant speed advantages over the conventional approach of implementing them in software. the mathematical algorithm of the square-root operator is described, and its applicability to an implementation in digital logic is presented. It also is shown that the square-root operator can be efficiently implemented without the need to resort to multiplications or divisions, which is advantageous in terms of both area and timing.

关键词： Arithmetic Signal processing algorithms field programmable gate arrays Algorithm design and analysis Hardware design languages Timing programmable logic arrays Application specific integrated circuits Convergence Laboratories

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