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Area-efficient implementation of a fast square root algorithm

Area-efficient implementation of a fast square root algorith...

引用

IEEE international Caracas conference on Devices, Circuits and Systems

作者： M.T. Tommiska Laboratory of Signal Processing and Computer Technology Helsinki University of Technology Finland

An area-efficient implementation of a fast-converging square-root algorithm is presented. the design of special arithmetic operations differs in many ways from the traditional tasks that digital designers are used to, and the role of parameterizability and mapping of mathematical algorithms onto digital hardware is discussed. Certain real-world applications requiring the use of the square-root operator are presented, and it is argued that implementing special arithmetic operations directly in hardware offers significant speed advantages over the conventional approach of implementing them in software. the mathematical algorithm of the square-root operator is described, and its applicability to an implementation in digital logic is presented. It also is shown that the square-root operator can be efficiently implemented without the need to resort to multiplications or divisions, which is advantageous in terms of both area and timing.

关键词： Arithmetic Signal processing algorithms field programmable gate arrays Algorithm design and analysis Hardware design languages Timing programmable logic arrays Application specific integrated circuits Convergence Laboratories

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An FPGA-based low-cost frame grabber for image processing applications

An FPGA-based low-cost frame grabber for image processing ap...

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IEEE international conference on Electronics, Circuits and Systems (ICECS)

作者： D. Xu S. Boussakta J.P. Bentley School of Science and Technology University of Teesside Middlesbrough UK School of Electronic and Electrical Engineering University of Leeds Leeds UK

ISBN: (纸本)0780365429

this paper presents a low-cost frame grabber, which was specifically designed as part of a real-time motion detection system for high-resolution images. the frame grabber is FPGA-based to minimise size of the PCB and improve reliability of the system. It also acts as a backend add-on card for an IBM-PC compatible. the experimental tests carried out on different machines show that the board implemented meets all specifications required by the system, and performs well. the captured frames are clear, well contrasted and jitter-free in both live and still video modes and their quality is comparable to that available from equivalent commercial systems.

关键词： field programmable gate arrays Image processing Control systems programmable logic arrays Hardware Displays Phase locked loops Real time systems Motion detection Image resolution

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9th international Workshop on field programmable logic and applications, FPL 1999

9th International Workshop on Field Programmable Logic and A...

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9th international Workshop on field programmable logic and applications, FPL 1999

ISBN: (纸本)3540664572

the proceedings contain 65 papers. the special focus in this conference is on Signal Processing and CAD Tools for DRL. the topics include: Reconfigurable processors for high-performance, embedded digital signal processing;a linear gammatone filterbank design for a model of the auditory system;a plug-in architecture for video processing;an interpretive simulation and visualization environment for dynamically reconfigurable systems;modelling and synthesis of configuration controllers for dynamically reconfigurable logic systems using the DCS CAD framework;optimal finite field multipliers for FPGAs;memory access optimization and RAM inference for pipeline vectorization;analysis and optimization of 3-D FPGA design parameters;ultra-fast placement for FPGAs;placement optimization based on global routing updating for system partitioning onto multi-FPGA mesh topologies;hierarchical interactive approach to partition large designs into FPGAs;logical-to-physical memory mapping for FPGAs with dual-port embedded arrays;a temporal floorplanning based CAD framework for dynamically reconfigurable logic systems;a bipartitioning algorithm for dynamic reconfigurable programmable logic;self controlling dynamic reconfiguration;an internet based development framework for reconfigurable computing;on tool integration in high-performance FPGA design flows;hardware-software codesign for dynamically reconfigurable architectures;serial hardware libraries for reconfigurable designs;reconfigurable computing in remote and harsh environments;communication synthesis for reconfigurable embedded systems and run-time parameterizable cores.

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Rapid FPGA prototyping of a DAB test data generator using protocol compiler 9th

Rapid FPGA prototyping of a DAB test data generator using pr...

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9th international Workshop on field programmable logic and applications, FPL 1999

作者： Feske, Klaus Scholz, Michael Döring, Günther Nareike, Denis FhG IIS Erlangen Department EAS Dresden Zeunerstr. 38 DresdenD-01069 Germany Dresden University of Technology Dept. Of Electrical Engineering Dresden Germany HTW Dresden Dept. Of Electrical Engineering Germany

ISBN: (纸本)3540664572

To enhance efficiency in FPGA based rapid prototyping of digital telecommunication applications, we incorporated modeling and synthesis facilities of the Protocol Compiler into a proved design flow. this paper focuses on domain specific modeling styles and synthesis strategies aiming at design improvement, changeability and reuse. We discuss design and implementation of a DAB (Digital Audio Broadcasting) Test Data Generator which produces hierarchical structured data streams according to the DAB protocol. Summarizing the results, we improved design quality and efficiency © Springer-Verlag Berlin Heidelberg 1999.

关键词： field programmable gate arrays (FPGA)

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Low cost approach for detecting, locating, and avoiding interconnect faults in FPGA-based reconfigurable systems

Low cost approach for detecting, locating, and avoiding inte...

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Proceedings of the 1999 12th international conference on VLSI Design

作者： Das, Debaleena Touba, Nur A. Univ of Texas Austin United States

An FPGA-based reconfigurable system may contain boards of FPGAs which are reconfigured for different applications and must work correctly. this paper presents a novel approach for rapidly testing the interconnect in the FPGAs each time the system is reconfigured. A low-cost configuration-dependent test method is used to both detect and locate faults in the interconnect. the `original configuration' is modified by only changing the logic function of the CLBs to form `test configurations' that can be used to quickly test the interconnect using the `walking-1' approach. the test procedure is rapid enough to be performed on the fly whenever the system is reconfigured. All stuck-at faults and bridging faults in the interconnect are guaranteed to be detected and located with a short test length. the fault location information can be used to reconfigure the system to avoid the faulty hardware.

关键词： field programmable gate arrays

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New custom computing machine dedicated to fast dynamic configuration applications 6

New custom computing machine dedicated to fast dynamic confi...

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6th IEEE international conference on Electronics, Circuits and Systems, ICECS 1999

作者： Rabel, G.E. Sawan, M. École Polytechnique de Montréal Department of Electrical and Computer Engineering Canada

ISBN: (纸本)0780356829

this paper presents a new custom computing machine (CCM) which combines a RISC core processor with rapidly reconfigurable FPGA, more closely than in any of the currently available custom computing machines, by a highly efficient flexible interface. the pyramidal architecture reconfigurable (PARC) resources are characterized by a fine-grained array of optimized logic blocks and hierarchical routing resources which can be totally configured in as short time as 25 μsec. the new RISC core processor is dedicated to fast dynamic configuration systems;it uses a reduced instruction set, hardware and software interrupts, etc. the interface provides to the PARC-FPGA the current state of the processor and allows the RISC processor direct access to the routing resources. It also provides direct programmable access between the PARC-FPGA and the RISC processor bank registers. this interface facilitates the sharing of hardware or software functions by the RISC core processor, and the reconfigurable logic resources. the circuit was designed using Synopsys (CAD) tools, VHDL hardware description language, and the 0.8 μm BiCMOS technology, to operate with a 40 MHz clock frequency. © 1999 IEEE.

关键词： Computer hardware description languages

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New custom computing machine dedicated to fast dynamic configuration applications

New custom computing machine dedicated to fast dynamic confi...

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IEEE international conference on Electronics, Circuits and Systems (ICECS)

作者： C.E. Rabel M. Sawan Department of Electrical and Computer Engineering École Polytechnique de Montréal Canada

this paper presents a new custom computing machine (CCM) which combines a RISC core processor with rapidly reconfigurable FPGA, more closely than in any of the currently available custom computing machines, by a highly efficient flexible interface. the pyramidal architecture reconfigurable (PARC) resources are characterized by a fine-grained array of optimized logic blocks and hierarchical routing resources which can be totally configured in as short time as 25 /spl mu/sec. the new RISC core processor is dedicated to fast dynamic configuration systems; it uses a reduced instruction set, hardware and software interrupts, etc. the interface provides to the PARC-FPGA the current state of the processor and allows the RISC processor direct access to the routing resources. It also provides direct programmable access between the PARC-FPGA and the RISC processor bank registers. this interface facilitates the sharing of hardware or software functions by the RISC core processor, and the reconfigurable logic resources. the circuit was designed using Synopsys (CAD) tools, VHDL hardware description language, and the 0.8 /spl mu/m BiCMOS technology, to operate with a 40 MHz clock frequency.

关键词： Reduced instruction set computing Computer interfaces logic arrays Reconfigurable logic Routing Hardware field programmable gate arrays Registers Circuits Design automation

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8th international Workshop on field-programmable logic and applications, FPL 1998

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8th international Workshop on field-programmable logic and applications, FPL 1998

ISBN: (纸本)3540649484

the proceedings contain 68 papers. the special focus in this conference is on Design Methods and General Aspects. the topics include: New CAD framework extends simulation of dynamically reconfigurable logic;a language for parametrised and reconfigurable hardware design;integrated development environment for logic synthesis based on dynamically reconfigurable FPGAs;designing for xilinx XC6200 FPGAs;perspectives of reconfigurable computing in research, industry and education;catalyst for new computing paradigms;run-time management of dynamically reconfigurable designs;acceleration of satisfiability algorithms by reconfigurable hardware;an optimized design flow for fast FPGA-based rapid prototyping;a knowledge-based system for prototyping on FPGAs;a rapid prototyping system based on java and FPGAs;prototyping new ILP architectures using FPGAs;fast floorplanning for FPGAs;a fault model for the configurable logic modules;reconfigurable hardware as shared resource in multipurpose computers;the bridge between high speed sensors and low speed computing;a reconfigurable engine for real-time video processing;an FPGA implementation of a magnetic bearing controller for mechatronic applications;exploiting contemporary memory techniques in reconfigurable accelerators;a platform for tractable virtual circuitry and reactive environment for runtime reconfiguration.

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programmable prototyping system for image processing 8th

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8th international Workshop on field-programmable logic and applications, FPL 1998

作者： Trost, Andrej Žemva, Andrej Zajc, Baldomir University of Ljubljana Tržaška 25 Ljubljana1000 Slovenia

ISBN: (纸本)3540649484

In this paper, we present a programmable prototyping system for hardware implementation of image processing algorithms. the system is composed of a PC, reconfigurable prototyping card with 2 FPGA circuits, microcontroller and memory circuit board. programmable devices are used for implementing the designed algorithm and the interface circuit for communication between the implemented design and the PC. the software for an automatic interface circuit synthesis allows users to design and implement digital circuits without specific knowledge of the structural details of the system. the implementation of the image processing chain is described to demonstrate the operation of the programmable system. © Springer-Verlag Berlin Heidelberg 1998.

关键词： Image processing

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A co-simulation concept for an efficient analysis of complex logic designs 8th

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8th international Workshop on field-programmable logic and applications, FPL 1998

作者： Fischer, J. Müller, C. Kurz, H. Institute of Semiconductor Electronics II Technical University of Aachen Sommerfeldstr. 24 AachenD-52056 Germany AMO GmbH Huyskensweg 25 AachenD-52074 Germany

ISBN: (纸本)3540649484

the focus of this paper is the presentation of our work on developing a novel co-simulation concept for synchronous logic designs. the growing complexity of programmable devices (FPGAs and CPLDs) requires complex test environments to find design and implementation errors as early in the design process as possible. In most cases it is the system environment that determines the performance requirements of the design and its behavior under dynamic workloads. Our approach takes advantage of the fact that the circuit design and simulation can be implemented with standard hardware description languages (HDLs). To model and simulate the system environment, however, we have used a state-of-the-art simulation language. Both simulations are tied together through a simple communication structure. the simulators constantly exchange state information, which provides dynamic feedback to simulate realistic workloads. As an application example we will describe how this concept was applied during the development of the controller logic for an optical high-speed network adapter. © Springer-Verlag Berlin Heidelberg 1998.

关键词： HIgh speed networks

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