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检索条件"任意字段=25th International Conference on Field Programmable Logic and Applications"

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Incremental routing in FPGAs

Incremental routing in FPGAs

引用

Annual IEEE international conference and Exhibit ASIC

作者： J.M. Emmert D. Bhatia University of Cincinnati Cincinnati OH USA

In this paper we present algorithms for incrementally routing circuits mapped to field-programmable gate arrays (FPGAs). the algorithms work well for ripping up and rerouting nets connected to small numbers of displaced logic blocks. Additionally the algorithms are sequential and compact, therefore making them ideal for embedding in hardware. Given an FPGA with a readable as well as writable configuration memory, these algorithms require no prior knowledge of the mapped circuit's netlist. Experimental results indicate our router works well for fault tolerance and other applications.

关键词： Routing field programmable gate arrays logic arrays Wiring Fault tolerance Hardware logic devices Switches Circuit faults Read-write memory

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Reconfigurable hardware systems

Reconfigurable hardware systems

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international conference on Semiconductor

作者： F. Rincon L. Teres CNM-CSIC Barcelona Spain

In this paper we'll make a short review, of the evolution of reconfigurable devices and their role inside reconfigurable systems, that we'll use to introduce an new emerging field: reconfigurable computing. We'll give the clues to understand its possibilities, as well as the applications that better suit to this techniques and systems in the midway between pure hardware and software solutions.

关键词： Hardware programmable logic arrays Switches logic devices EPROM Fuses logic programming Random access memory Switching circuits Reconfigurable logic

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High-speed neural network based classifier for real-time application

High-speed neural network based classifier for real-time app...

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international conference on Signal Processing Proceedings (ICSP)

作者： Yuk Ying Chung Man To Wong N.W. Bergmann Space Centre for Satellite Navigation School of Electrical and Electronic Systems Engineering The Queen's Medical Center Brisbane Australia Neurocomputing Research Centre School of Computing Science The Queen's Medical Center Brisbane Australia

this paper describes how to implement a partially connected neural network by a Giga-Ops Spectrum G800 FPGA (field programmable gate arrays)-based custom computer which consists of up to 32 Xilinx XC4010 logic chips. From the training data, a decision tree is generated by the classifier program C4.5. the tree is then used to initialise the neural network to a nearly optimum configuration. this initialised partially connected neural network is then trained by training data. the trained neural network is then implemented by our custom computer system. this implementation requires fewer connections and can provide a very-high-speed classifier for many real-time image recognition applications.

关键词： Neural networks Decision trees Neurons field programmable gate arrays Computer networks Space technology Application software Real time systems Australia programmable logic arrays

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Circuit design using resonant tunneling diodes

Circuit design using resonant tunneling diodes

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11th international conference on VLSI Design

作者： Mazumder, P Kulkarni, S Bhattacharya, M Gonzalez, A Univ Michigan Dept Elect Engn & Comp Sci Ann Arbor MI 48109 USA

ISBN: (纸本)0818682248

Picosecond switching speeds and folded current voltage characteristics have made quantum tunneling devices promising alternatives for high-speed a nd compact VLSI circuit design. this paper describes new bistable digital logic circuit topologies that use resonant tunneling diodes (RTDs) in conjunction with heterojunction bipolar transistors (HBTs) and modulation-doped field effect transistors (MODFETs). the designed circuits include a single-gate. self-latching MAJORITY function besides basic NAND, NOR and inverter gates. the application of these circuits in the design of high-performance adders and parallel correlators is discussed. We also review multiple-valued logic (MVL) applications of RTDs that achieve significant compaction in terms of device count over comparable binary logic implementations in conventional technologies. these include a four-valued 4:1 multiplexer using 13 resonant tunneling bipolar transistors (RTBTs) and HBTs, a mask programmable four-valued, single-input gate using 4 RTDs and 14 HBTs, and a four-step countdown circuit using 1 RTD and 3 HBTs.

关键词： logic design

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7th international Workshop on field-programmable logic and applications, FPL 1997

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7th international Workshop on field programmable logic and applications, FPL 1997

ISBN: (纸本)3540634657

the proceedings contain 51 papers. the special focus in this conference is on Devices and Architectures. the topics include: Multicontext dynamic reconfiguration and real time probing on a novel mixed signal programmable device with on-chip microprocessor;CAD-oriented FPGA and dedicated CAD system for telecommunications;a three dimensional FPGA architecture, its fabrication, and design tools;extending dynamic circuit switching to meet the challenges of new FPGA architectures;performance evaluation of a full speed PCI initiator and target subsystem using FPGAs;implementation of pipelined multipliers on xilinx FPGAs;the XC6200DS development system;thermal monitoring on FPGAs using ring-oscillators;a reconfigurable approach to low cost media processing;a flexible platform for codesign and dynamic reconfigurable computing research;stream synthesis for a wormhole run-time reconfigurable platform;pipeline morphing and virtual pipelines;parallel graph colouring using FPGAs;run-time compaction of FPGA designs;partial reconfiguration of FPGA mapped designs with applications to fault tolerance and yield enhancement;a case study of partially evaluated hardware circuits;run-time parameterised circuits for the xilinx XC6200;automatic identification of swappable logic units in XC6200 circuitry;towards an expert system for a priori estimation of reconfiguration latency in dynamically reconfigurable logic;exploiting reconfigurability through domain-specific systems;technology mapping by binate covering;a new packing, placement and routing tool for FPGA research;technology mapping of heterogeneous LUT-based FPGAs and technology-driven FSM partitioning for synthesis of large sequential circuits targeting lookup-table based FPGAs.

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Technology mapping of heterogeneous LUT-based FPGAs 7th

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7th international Workshop on field programmable logic and applications, FPL 1997

作者： Inuani, Maurice Kilavuka Saul, Jonathan Oxford University Computing Laboratory Wolfson Building Parks Road OxfordOX1 3QD United Kingdom

ISBN: (纸本)3540634657

New techniques have been developed for the technology mapping of FPGAs containing more than one size of look-up table. the Xilinx 4000 series is one such family of devices. these have a very large share of the FPGA market, and yet the associated technology mapping problem has hardly been addressed in the literature. Our method extends the standard techniques of functional decomposition and network covering. For the decomposition, we have extended the conventional binpacking (cube-packing) algorithms so that it produces two sizes of bins. We have also enhanced it to explore several packing possibilities, and include cube division and cascading of nodes. the covering step is based on the concept of flow networks and cut-computation. We devised a theory that reduces the flow network sizes so that a dynamic programming approach can be used to compute the feasible cuts in the network. An iterative selection algorithm can then be used to compute the set cover of the network. Experimental results show good performances for the Xilinx 4K devices (about 25% improvement over MOFL and 10% over comparable algorithms in SIS in terms of CLBs). © Springer-Verlag Berlin Heidelberg 1997.

关键词： field programmable gate arrays (FPGA)

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Applying functional decomposition for depth minimal technology mapping of multiplexer based FPGAs

Applying functional decomposition for depth minimal technolo...

引用

Annual IEEE international conference and Exhibit ASIC

作者： Chingwei Yeh EE Department National Chung Cheng University Chiayi Taiwan

ISBN: (纸本)0780342836

Functional decomposition has undergone intensive study in recent literature and gained great success in technology mapping for lookup-table based FPGAs. Yet none has ever attempted at extending such success to other applications. In this work, we move one step further by choosing the multiplexer based FPGAs as the new test bed. Using a typical algorithmic framework and the benchmark test set, we show that functional decomposition can be easily adapted to reduce the logic depth of the mapped network without incurring massive area penalty.

关键词： Multiplexing field programmable gate arrays Data structures Boolean functions logic programming Dynamic programming logic testing logic arrays Libraries Benchmark testing

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6th international Workshop on field-programmable logic and applications, FPL 1996

6th International Workshop on Field-Programmable Logic and A...

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6th international Workshop on field-programmable logic and applications, FPL 1996

ISBN: (纸本)9783540617303

the proceedings contain 50 papers. the special focus in this conference is on High-level Design I, New Software and Hardware Development Tools. the topics include: Portable pipeline synthesis for FCCMs;a framework for developing parametrised FPGA libraries;co-evaluation environment for FPGA architecture and CAD system;an universal CLA adder generator for SRAM-based FPGAs;a data driven computer on a virtual hardware;custom computing machines vs. hardware/software codesign;reconfigurable and adaptive computing environment;computing 2-D DFTs using FPGAs;computer aided prototyping partitioning for Xilinx FPGAs, a hierarchical partitioning tool for rapid prototyping;architectural synthesis and efficient circuit implementation for field programmable gate arrays;reconfigurable pipelined datapath;solving satisfiability problems on FPGAs;FPGA implementation of the block-matching algorithm for motion estimation in image coding;parallel CRC computation in FPGAs;coherent demodulation with FPGAs;the trianus system and its application to custom computing;flexible codesign target architecture for early prototyping of CMIST systems;a reconfigurable multiprocessor testbed;a slow motion engine for the analysis of FPGA-based prototypes;implementing reconfigurable datapaths in FPGAs for adaptive filter design;a fast constant coefficient multiplier for the XC6200;key issues for user acceptance of FPGA design tools;reconfigurable DSP demonstrators for the development of spacecraft payload processors;reconfigurable logic based fibre channel network card with sub 2 micro-second raw latency;an instruction-level custom-configurable processor;architectural synthesis techniques for dynamically reconfigurable logic and fast reconfigurable crossbar switching in FPGAs.

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Key issues for user acceptance of FPGA design tools 6th

Key issues for user acceptance of FPGA design tools

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6th international Workshop on field-programmable logic and applications, FPL 1996

作者： Ditzinger, Albrecht Remme, Ralph ISDATA GmbH Daimlerstr. 51 KarlsruheD-76185 Germany

ISBN: (纸本)9783540617303

there is hardly a field in the EDA community where latest research activities and real use of tools is so divergent as in the case of synthesis for FPGAs. Latest research work for FPGA synthesis and also available tools are quickly proceeding towards the third level of synthesis, behavioral synthesis. On the other hand, the majority of FPGA designs is still done today using schematic entry. this paper first enumerates some potential reasons for the reluctance of FPGA designers to use synthesis tools. After that, some important prerequisites are discussed which the author considers absolutely necessary to improve the acceptance of synthesis tools amongst FPGA designers. © Springer-Verlag Berlin Heidelberg 1996.

关键词： field programmable gate arrays (FPGA)

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Hardware evolution at function level 4th

Hardware evolution at function level

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international conference on Evolutionary Computation - 4th international conference on Parallel Problem Solving from Nature, PPSN 1996

作者： Murakawa, Masahiro Yoshizawa, Shuji Kajitani, Isamu Furuya, Tatsumi Iwata, Masaya Higuchi, Tetsuya University of Tokyo 7-3-1Hongo Bunkyo Tokyo Japan University of Tsukuba 1-1-t Tennoudai TsukubaIbaraki Japan Toho University 2-2-1 Miyama FunabashiChiba Japan Electrotechnical Laboratory 1-1-4 Umezono TsukubaIbaraki Japan

ISBN: (纸本)354061723X

this paper describes a function-level Evolvable Hardware (EHW). EHW is hardware which is built on programmable logic devices (e.g. PLD and FPGA) and whose architecture can be reconfigured by using a genetic learning to adapt to new unknown environments in real time. It is demonstrated that the function-level hardware evolution can attain much higher performances than the gate-level evolution, in neural network applications (e.g. two-spiral). VLSI architecture of the functionbased FPGA dedicated to function level evolution is also described. © 1996, Springer-Verlag. All rights reserved.

关键词： field programmable gate arrays (FPGA)

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