检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

1,813 篇 会议
28 篇 期刊文献
5 册 图书

馆藏范围

1,846 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

1,201 篇 工学
- 1,018 篇 计算机科学与技术...
- 707 篇 软件工程
- 387 篇 电气工程
- 186 篇 电子科学与技术（可...
- 62 篇 信息与通信工程
- 60 篇 控制科学与工程
- 26 篇 机械工程
- 26 篇 仪器科学与技术
- 25 篇 动力工程及工程热...
- 24 篇 建筑学
- 16 篇 土木工程
- 14 篇 生物工程
- 11 篇 核科学与技术
- 10 篇 材料科学与工程（可...
- 9 篇 光学工程
- 8 篇 生物医学工程（可授...
- 8 篇 安全科学与工程
- 6 篇 化学工程与技术
- 6 篇 交通运输工程
146 篇 理学
- 97 篇 数学
- 33 篇 物理学
- 16 篇 生物学
- 14 篇 系统科学
- 10 篇 统计学（可授理学、...
- 6 篇 化学
52 篇 管理学
- 39 篇 管理科学与工程(可...
- 17 篇 工商管理
- 15 篇 图书情报与档案管...
14 篇 法学
- 12 篇 社会学
9 篇 经济学
- 9 篇 应用经济学
8 篇 医学
6 篇 农学
4 篇 军事学
2 篇 教育学

主题

815 篇 field programmab...
670 篇 field programmab...
271 篇 hardware
154 篇 computer archite...
119 篇 logic gates
111 篇 table lookup
94 篇 clocks
83 篇 throughput
78 篇 random access me...
72 篇 routing
71 篇 acceleration
71 篇 software
66 篇 optimization
63 篇 kernel
61 篇 delays
52 篇 registers
52 篇 logic
49 篇 switches
46 篇 algorithm design...
45 篇 computational mo...

机构

15 篇 univ toronto dep...
9 篇 department of co...
9 篇 imperial coll lo...
8 篇 ecole polytech f...
7 篇 univ british col...
7 篇 school of comput...
7 篇 brigham young un...
7 篇 imperial coll lo...
7 篇 tokyo inst techn...
6 篇 univ tsukuba tsu...
6 篇 university of ch...
6 篇 department of el...
6 篇 univ warwick sch...
6 篇 xilinx inc san j...
5 篇 univ manchester ...
5 篇 department of el...
5 篇 univ toronto dep...
5 篇 swiss fed inst t...
5 篇 xilinx inc 2100 ...
5 篇 altera corp san ...

作者

33 篇 luk wayne
21 篇 maruyama tsutomu
16 篇 wayne luk
16 篇 koch dirk
12 篇 wilton steven j....
12 篇 betz vaughn
12 篇 ienne paolo
11 篇 fahmy suhaib a.
11 篇 cheung peter y. ...
10 篇 vaughn betz
9 篇 constantinides g...
8 篇 suhaib a. fahmy
8 篇 prasanna viktor ...
8 篇 chow paul
8 篇 glesner manfred
8 篇 amano hideharu
8 篇 akash kumar
7 篇 kapre nachiket
7 篇 alonso gustavo
7 篇 hutchings brad

语言

1,838 篇 英文
8 篇 其他

检索条件"任意字段=25th International Conference on Field Programmable Logic and Applications"

共 1846 条记录，以下是181-190 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Efficient Table-Based Polynomial on FPGA 39

Efficient Table-Based Polynomial on FPGA

引用

39th IEEE international conference on Computer Design ICCD)

作者： Barbone, Marco Kwaadgras, Bas W. Oelfke, Uwe Luk, Wayne Gaydadjiev, Georgi Imperial Coll London Dept Comp London England Univ Groningen Bernoulli Inst Groningen Netherlands Inst Canc Res Joint Dept Phys London England Royal Marsden NHS Fdn Trust London England Maxeler Technol London England

ISBN: (纸本)9781665432191

field programmable Gate Arrays (FPGAs) are gaining popularity in the context of scientific computing due to the recent advances of High-Level Synthesis (HLS) tool-chains for customised hardware implementations combined with the increase in computing capabilities of modern FPGAs. As a result, developers are able to implement more complex scientific workloads which often require the evaluation of univariate numerical functions. In this study, we propose a methodology for table-based polynomial interpolation aiming at producing area-efficient implementations of such functions on FPGAs achieving the same accuracy and at similar performance as direct implementations. We also provide a rigorous error analysis to guarantee the correctness of the results. Our methodology covers the forecast of resource utilisation of the polynomial interpolator and, based on the characteristics of the function, guides the developer to the most area-efficient FPGA implementation. Our experiments show that in the case of a radiation spectrum of a Black Body application based on evaluating Planck's Law, it is possible to reduce resource utilisation by up to 90% when compared to direct implementations not using table-based methods. Moreover, when only the kernels are considered, our method uses up to two orders of magnitude fewer resources with no performance penalties. Based on previous more theoretical works, our study investigates practical applications of table-based methods in the context of high performance and scientific computing where it is used to implement common but more complex functions than the elementary functions widely studied in the related literature.

关键词： Interpolation Scientific computing Error analysis conferences logic gates Hardware Resource management

来源：评论

学校读者我要写书评

暂无评论

Design and Implementation of Low Power Posit Arithmetic Unit for Efficient Hardware Accelerators

Design and Implementation of Low Power Posit Arithmetic Unit...

引用

Japan-Egypt international conference on Electronics, Communications and Computers (JEC-ECC)

作者： Mohammed Essam Ahmed Shalaby Mohamed Taher Computer and Systems Engineering Department Ain Shams University Cairo Egypt Computer Science Department Benha University Benha Egypt

ISBN: (纸本)9781665464642

there is an increasing interest in hardware accelerators, both in academia and industry. the industry invests in application-level accelerators, like Graphics Processing Units (GPUs) or field programmable Gate Array (FPGA) accelerators connected to the PCIe bus. Hardware accelerators outperform general purpose Central Processing Units (CPUs) in terms of power consumption and performance. Hardware accelerators seek to optimize arithmetic operations, since it is the heart of the computation circuitry in different algorithms and applications. In this context, posit is proposed to replace IEEE Standard 754-2008 floating point and offers more efficient arithmetic units in terms of accuracy and Power-Performance-Area (PPA) matrix. In this paper, we introduce a low power Verilog HDL design and implementation of Posit Arithmetic Unit (PAU) for efficient hardware accelerators. Our regular proposed PAU is synthesized on Xilinx ZYNQ-7000. the results show34% area improvement and 14% power saving, while our compact PAU achieves 25% area reduction and 45% power saving.

关键词： Industries Power demand logic gates IEEE Standards Resource management Hardware design languages Hardware acceleration

来源：评论

学校读者我要写书评

暂无评论

FPGA Implementation of Digital Channelizer

FPGA Implementation of Digital Channelizer

引用

IEEE Signal Processing and Communications applications (SIU)

作者： Kadir Ayhan Alptekin Pamuk Bekir Ahmet Doğ rusö z Haberle&#x015F me ve Bilgi Teknolojiler Sekt&#x00F6 r Ba&#x015F kanl&#x0131 &#x011F &#x0131 Aselsan A.&#x015E . Ankara T&#x00FC rkiye

ISBN: (数字)9781665450928

ISBN: (纸本)9781665450935

In this paper, designing and implementing process of a device on space-grade FPGA (field programmable Gate Array), which channelizes from signals that have 25KHz bandwidth in 30 MHz band around of specific center frequency to band around another specific center frequency, is described detailly. DDS (Direct Digital Synthesis) algorithm, which is used for carrying the signals from wanted frequency to DC is presented. DDS algorithms are presented comparatively in terms of utilization of FPGA resources, and performances. Designed and implemented modules that reduce utilization of FPGA resources, such that; poly-phase filters, CIC (Cascaded Integrator Comb) filters, FIR filters that suppress out of 25KHz, and other signal processing techniques are explained.

关键词： Frequency synthesizers Finite impulse response filters Array signal processing Signal processing algorithms Bandwidth logic gates Filtering algorithms

来源：评论

学校读者我要写书评

暂无评论

Progressive Learning Algorithm for Efficient Person Re- Identification

Progressive Learning Algorithm for Efficient Person Re- Iden...

引用

international conference on Pattern Recognition

作者： Zhen Li Hanyang Shao Liang Niu Nian Xue Shanghai Grandhonor Information Technology Co.Ltd Nanjing University of Aeronautics and Astronautic Shanghai China Shanghai Grandhonor Information Technology Co.Ltd Shanghai China New York University New York University Abu Dhabi New York NY

ISBN: (纸本)9781728188089;9781728188096

this paper studies the problem of Person Re-Identification (ReID) for large-scale applications. Recent research efforts have been devoted to building complicated part models, which introduce considerably high computational cost and memory consumption, inhibiting its practicability in large-scale applications. this paper aims to develop a novel learning strategy to find efficient feature embeddings while maintaining the balance of accuracy and model complexity. More specifically, we find by enhancing the classical triplet loss together with cross-entropy loss, our method can explore the hard examples and build a discriminant feature embedding yet compact enough for large-scale applications. Our method is carried out progressively using Bayesian optimization, and we call it the Progressive Learning Algorithm (PLA). Extensive experiments on three large-scale datasets show that our PLA is comparable or better than the-state-of-the-arts. Especially, on the challenging Market-ISOI dataset, we achieve Rank-1=94.7%/mAP=89.4% while saving at least 30 % parameters than strong part models.

关键词： Computational modeling Memory management Buildings programmable logic arrays Market research Inference algorithms Computational efficiency

来源：评论

学校读者我要写书评

暂无评论

Multi-channel high-linearity time-to-digital converters in 20 nm and 28 nm FPGAs for LiDAR applications 6

Multi-channel high-linearity time-to-digital converters in 2...

引用

6th international conference on Event-Based Control, Communication, and Signal Processing (EBCCSP)

作者： Xie, Wujun Chen, Haochang Zang, Zhenya Li, David Day-Uei Univ Strathclyde Fac Sci Glasgow G4 0RE Lanark Scotland

ISBN: (纸本)9781728195810

this paper proposes a new calibration method, the mixed-binning method, to pursue a TDC with high linearity in field-programmable gate arrays (FPGAs). this method can reduce the nonlinearity caused by large clock skews in FPGAs efficiently. therefore, a wide dynamic range tapped delay line (TDL) TDC has been developed with maintained linearity. We evaluated this method in Xilinx 20nm UltraScale FPGAs and Xilinx 28nm Virtex-7 FPGAs. Results conduct that this method is perfectly suitable for driverless vehicle applications which require high linearity with an acceptable resolution. the proposed method also has great potentials for multi-channel applications, due to the low logic resource consumption. For a quick proof-of-concept demonstration, an 8-channel solution has also been implemented. It can be further extended to a 64-channel version soon.

关键词： Carry chains field-programmable gate array (FPGA) time-of-flight time-to-digital converter (TDC) Automatic Vehicle

来源：评论

学校读者我要写书评

暂无评论

Overview of FPGA and CPLD Device Testing Techniques Based on ATE

Overview of FPGA and CPLD Device Testing Techniques Based on...

引用

IEEE international conference on Circuits and Systems (ICCS)

作者： Weikun Xie Xiaohui Lin Houjun Wang Kaihong Zhang University of Electronic and Technology of China Chengdu China The 58th Research Institute of China Electronics Technology Corporation Wuxi China

ISBN: (纸本)9781665429634

Aiming at the test and development of programmable logic devices, this article focuses on the differences in FPGA test configurations from vendors, the differences in CPLD test configurations from vendors, and the differences between FPGA and CPLD device testing. Based on these analysis conclusions, it will play a certain guiding role for subsequent test development and engineering applications.

关键词： Circuits and systems conferences programmable logic devices field programmable gate arrays Testing

来源：评论

学校读者我要写书评

暂无评论

Virtualizing FPGAs in the Cloud 20

Virtualizing FPGAs in the Cloud

引用

25th international conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS)

作者： Zha, Yue Li, Jing Univ Penn Philadelphia PA 19104 USA

ISBN: (纸本)9781450371025

field-programmable Gate Arrays (FPGAs) have been integrated into the cloud infrastructure to enhance its computing performance by supporting on-demand acceleration. However, system support for FPGAs in the context of the cloud environment is still in its infancy with two major limitations, i.e., the inefficient runtime management due to the tight coupling between compilation and resource allocation, and the high programming complexity when exploiting scale-out acceleration. the root cause is that FPGA resources are not virtualized. In this paper, we propose a full-stack solution, namely ViTAL, to address the aforementioned limitations by virtualizing FPGA resources. Specifically, ViTAL provides a homogeneous abstraction to decouple the compilation and resource allocation. applications are offline compiled onto the abstraction, while the resource allocation is dynamically determined at runtime. Enabled by a latency-insensitive communication interface, applications can be mapped flexibly onto either one FPGA or multiple FPGAs to maximize the resource utilization and the aggregated system throughput. Meanwhile, ViTAL creates an illusion of a single and large FPGA to users, thereby reducing the programming complexity and supporting scale-out acceleration. Moreover, ViTAL also provides virtualization support for peripheral components (e.g., on-board DRAM and Ethernet), as well as protection and isolation support to ensure a secure execution in the multi-user cloud environment. We evaluate ViTAL on a real system-an FPGA cluster composed of the latest Xilinx UltraScale+ FPGAs (XCVU37P). the results show that, compared with the existing management method, ViTAL enables fine-grained resource sharing and reduces the response time by 82% on average (improving Quality-of-Service) with a marginal virtualization overhead. Moreover, ViTAL also reduces the response time by 25% compared to AmorphOS (operating in high-throughput mode), a recently proposed FPGA virtualization method.

关键词： scale-out acceleration system abstraction compilation framework cloud computing field-programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

Hardware Accelerator for Edge Detection 24

Hardware Accelerator for Edge Detection

引用

24th IEEE international conference on Intelligent Engineering Systems (INES)

作者： Kurdi, Aous H. Grantner, Janos L. Abdel-Qader, Ikhlas Western Michigan Univ Dept Elect & Comp Engn Kalamazoo MI 49008 USA

ISBN: (纸本)9781728110592

Hardware accelerators have been recently proposed for computationally extensive applications like real-time video image processing systems. Contemporary hardware accelerators are implemented by using either field programmable Gate Array (FPGA) or System-on-Chip (SoC) devices. Edge detection is a fundamental task for any image processing system. In this paper, a pipelined architecture for a fuzzy logic edge detection system is proposed. the system has been implemented and tested on various Xilinx 7 Series devices. the hardware accelerator core utilizes a pipeline of seven stages. Depending on the available resources the accelerator system can be made up of several cores operating simultaneously. A single-core implementation of the system can process a 1080P HD test frame at a rate of about 45 frames per second. It outperforms its software counterpart by a factor of ten thousand.

关键词： Fuzzy logic-based edge detection pipelined hardware accelerator

来源：评论

学校读者我要写书评

暂无评论

FPGA based Optimized Decimator using Distributed Arithmetic Algorithm for Wireless applications

FPGA based Optimized Decimator using Distributed Arithmetic ...

引用

international conference for Convergence of Technology (I2CT)

作者： Lajwanti Singh Geetanjali Rajesh Mehra Banasthali Vidyapeeth University Rajasthan India NITTTR Chandigarh India

In this paper, FPGA based enhanced decimator utilizing DA is introduced for remote applications for giving better answers for inspecting rate modifications. the proposed decimator is planned utilizing Poly stage disintegration strategy. Circulated Arithmetic (DA) Algorithm which is a multiplier free methodology is utilized for devouring less equipment assets and to bring about a rapid decimator. Equipment multifaceted nature is decreased by utilizing advanced Look up Table (LUT) apportioning. the proposed configuration shows an improvement of 6.2-14% in speed. By devouring practically same number of cuts and F/Flops, number of LUTs is diminished by 11.95-17.63% demonstrating prudent arrangement. At long last the created decimator configuration is mimicked and incorporated on Virtex 2 Pro based objective field programmable Gate Array (FPGA).

关键词： Wireless communication Correlation logic gates Tools Table lookup field programmable gate arrays Convergence

来源：评论

学校读者我要写书评

暂无评论

Reduced frequency and area efficient for streaming applications using clock gating and BUFGCE technology 4th

Reduced frequency and area efficient for streaming applicati...

引用

4th international conference on Research in Intelligent and Computing in Engineering, RICE 2019

作者： Lavanya, N. Harikrishna, B. Kalpana, K. Department of ECE CMR Engineering College Hyderabad India

ISBN: (纸本)9789811527791

Reduced frequency and area-efficient streaming applications using clock gating and BUFGCE technique are presented in the paper. the clock-gating methodology consists of a different microcontroller, logic gates, flip-flop, and buffer. We used four controllers and a logic gate. the experimental results show that area is reduced to 26%, frequency 630.14 MHz, and thereby reducing the dynamic power without any fall in output data. © Springer Nature Singapore Pte Ltd. 2020.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共185页 << < 15 16 17 18 19 20 21 22 23 24 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：