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检索条件"任意字段=25th International Conference on Field Programmable Logic and Applications"

共 1846 条记录，以下是191-200 订阅

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Demonstration of Flow-in-Cloud: A multi-FPGA system 29

Demonstration of Flow-in-Cloud: A multi-FPGA system

引用

29th international conference on field-programmable logic and applications (FPL)

作者： Hironaka, Kazuei Iizuka, Kensuke Ben Ahmed, Akram Ullah, M. M. Imdad Yamauchi, Yugo Sun, Yuxi Yamakura, Miho Hiruma, Aoi Amano, Hideharu Keio Univ Dept Informat & Comp Sci Yokohama Kanagawa Japan

Flow-in-Cloud(FiC) is an acceleration platform designed to make a virtual monolithic large FPGA image from a number of mid-range economical FPGAs. We will show the live demonstration of the acceleration example of FiC... 详细信息

ISBN: (纸本)9781728148847

关键词： field programmable gate arrays Switches Clocks Servers Acceleration Bandwidth Prototypes

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Formal Methods of FPGA Project Verification Flow

Formal Methods of FPGA Project Verification Flow

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IEEE international Workshop on Intelligent Data Acquisition and Advanced Computing Systems: Technology and applications

作者： Serhii Naumenko Viktoriia Moskalets Oleg Odarushchenko Elena Odarushchenko Volodymyr Peschanenko Larysa Degtyareva Oleksandr Letychevskyi Poltava State Agrarian Academy Poltava Ukraine Radics LLC Kropyvnytskiy Ukraine Kherson State University Kherson Ukraine V.M.Glushkov Institute of Cybernetics of the NAS of Ukraine Kyiv Ukraine

ISBN: (纸本)9781665426060

FPGA technology for developing safety-based PLCs for industrial applications (for example NPP I&C) became more popular. One of the main part of FPGA-based I&C system lifecycle is verification. FPGA Project Verification main stages are described. Verification influence on product development time, cost and quality are described. the article presents a new approach to performing the functional testing stage. this approach is based on the use of formal algebraic methods. the main advantage of using this approach is the increase in testing efficiency due to the use of the procedure for automatic generation of test cases. More than 10 years' experience of verification approaches of Radics LLC verification team is presented.

关键词： Costs Data acquisition programmable logic arrays logic gates Product development Data models field programmable gate arrays

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TensorFlow to Cloud FPGAs: Tradeoffs for Accelerating Deep Neural Networks 29

TensorFlow to Cloud FPGAs: Tradeoffs for Accelerating Deep N...

引用

29th international conference on field-programmable logic and applications (FPL)

作者： Hadjis, Stefan Olukotun, Kunle Stanford Univ Dept Comp Sci Stanford CA 94305 USA

ISBN: (纸本)9781728148847

We present the first open-source TensorFlow to FPGA tool capable of running state-of-the-art DNNs. Running TensorFlow on the Amazon cloud FPGA instances, we provide competitive performance and higher accuracy compared to a proprietary tool, thus providing a public framework for research exploration in the DNN inference space. We also detail the optimizations needed to map modern DNN frameworks to FPGAs, provide novel analysis of design tradeoffs for FPGA DNN accelerators and present experiments across a range of DNNs.

关键词： Optimization field programmable gate arrays Hardware Tools Memory management Convolution

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the FOS (FPGA Operating System) Demo 29

The FOS (FPGA Operating System) Demo

引用

29th international conference on field-programmable logic and applications (FPL)

作者： Vaishnav, Anuj Khoa Dang Pham Manev, Kristiyan Koch, Dirk Univ Manchester Sch Comp Sci Manchester Lancs England

ISBN: (纸本)9781728148847

With the introduction of Zynq FPGAs that provide an ARM SoC with an attached FPGA fabric, it is possible to build complex software-centric systems that are software and hardware programmable. To harness the full potential of this approach, we developed FOS an FPGA Operating System which is built on open-source FPGA community and Xilinx vendor components. A distinct feature shown in this demo is a heterogeneous resource elastic scheduler that can dynamically and automatically adjust the allocation of tasks to hardware and software resources with respect to the present load scenario. We will also show the FOS ecosystem that allows easily implementing relocatable partially reconfigurable modules directly from RTL or HLS.

关键词： field programmable gate arrays Hardware Task analysis Runtime Operating systems Fabrics

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Software and Hardware Co-design for Low-Power HPC Platforms 1

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34th international conference on High Performance Computing (ISC High Performance)

作者： Ploumidis, Manolis Kallimanis, Nikolaos D. Asiminakis, Marios Chrysos, Nikos Xirouchakis, Pantelis Gianoudis, Michalis Tzanakis, Leandros Dimou, Nikolaos Psistakis, Antonis Peristerakis, Panagiotis Kalokairinos, Giorgos Papaefstathiou, Vassilis Katevenis, Manolis Fdn Res & Technol Hellas FORTH Iraklion Crete Greece

ISBN: (数字)9783030343569

ISBN: (纸本)9783030343569;9783030343552

In order to keep an HPC cluster viable in terms of economy, serious cost limitations on the hardware and software deployment should be considered, prompting researchers to reconsider the design of modern HPC platforms. In this paper we present a cross-layer communication architecture suitable for emerging HPC platforms based on heterogeneous multiprocessors. We propose simple hardware primitives that enable protected, reliable and virtualized, user-level communication that can easily be integrate in the same package with the processing unit. Using an efficient user-space software stack the proposed architecture provides efficient, low-latency communication mechanisms to HPC applications. Our implementation of the MPI standard that exploits the aforementioned capabilities delivers point-to-point and collective primitives with low overheads, including an eager protocol with end-to-end latency of 1.4 mu s. We port and evaluate our communication stack using real HPC applications in a cluster of 128 ARMv8 processors that are tightly coupled with FPGA logic. the network interface primitives occupy less than 25% of the FPGA logic and only 3 Mbits of SRAM while they can easily saturate the 16 Gb/s links in our platform.

关键词： field programmable gate arrays (FPGA)

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Network Intrusion Detection Using Neural Networks on FPGA SoCs 29

Network Intrusion Detection Using Neural Networks on FPGA So...

引用

29th international conference on field-programmable logic and applications (FPL)

作者： Ioannou, Lenos Fahmy, Suhaib A. Univ Warwick Sch Engn Coventry W Midlands England

ISBN: (纸本)9781728148847

Network security is increasing in importance as systems become more interconnected. Much research has been conducted on large appliances for network security, but these do not scale well to lightweight systems such as those used in the Internet of things (IoT). Meanwhile, the low power processors used in IoT devices do not have the required performance for detailed packet analysis. We present an approach for network intrusion detection using neural networks, implemented on FPGA SoC devices that can achieve the required performance on embedded systems. the design is flexible, allowing model updates in order to adapt to emerging attacks.

关键词： Artificial neural networks Feature extraction Security Training field programmable gate arrays Internet of things

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Tinsel: a manythread overlay for FPGA clusters 29

Tinsel: a manythread overlay for FPGA clusters

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29th international conference on field-programmable logic and applications (FPL)

作者： Naylor, Matthew Moore, Simon W. thomas, David Univ Cambridge Cambridge England Imperial Coll London London England

ISBN: (纸本)9781728148847

Commodity FPGA boards with advanced networking facilities have great potential in the construction of high-performance compute clusters that scale. However, low-level design tools and long synthesis times are major barriers to productivity for application developers. In this paper, we explore the potential of a distributed soft-processor overlay, programmed in software at a high-level of abstraction, to deliver a useful level of performance for FPGA clusters. In particular, we demonstrate the use of hardware multhreading to achieve a fast, space-efficient, high-throughput overlay, and compare a 12-FPGA instance of it (12,288 RISC-V threads) against a conventional Xeon cluster on the problem of distributed graph processing.

关键词： Message systems field programmable gate arrays Random access memory Hardware Software Pipelines throughput

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Low-level Loop Analysis and Pipelining of applications mapped to Xilinx FPGAs 29

Low-level Loop Analysis and Pipelining of Applications mappe...

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29th international conference on field-programmable logic and applications (FPL)

作者： Omidian, Hossein Lemieux, Guy G. F. Xilinx Inc San Jose CA 95124 USA Univ British Columbia Vancouver BC Canada

ISBN: (纸本)9781728148847

In this paper we investigate using low-level loop analysis to identify common loop patterns in the netlist generated by the synthesis flow and use loop optimization techniques to increase Fmax of applications implemented on Xilinx FPGAs. Ordinarily, feed-forward paths in the netlist can be easily pipelined. the focus of this study is only sequential loops (with feedback cycles) that are more challenging to optimize. We show that, using low-level loop analysis, we can improve Fmax on average by 57% and achieve an average Fmax of 714MHz across seven industrial designs. Using aggressive loop combining, we also show that we can save 18% area on average while still improving the Fmax by 15% to 41% on four of the seven designs.

关键词： Low-level Loop Analysis FPGA Pipeline Loop Transformation

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Research and implementation of an automatic simulation tool 7

Research and implementation of an automatic simulation tool

引用

7th international conference on Dependable Systems and their applications, DSA 2020

作者： Tang, Liu Li, You Wang, Hongwei Zhao, Huan Ma, Luze Sun, Yuming Beijing Sunwise Information Technology Ltd. China

ISBN: (纸本)9780738124223

With the rapidly increasing of space missions, FPGA is more widely used for its ability of single chip approaching 10 million gates of logic and 10 million bits of memory. More and more challenges are posed to FPGA design and verification, with the characteristics of a tight schedule, a burdensome task, momentous responsibilities, etc. A reusable and robust environment for verification is needed to improve the efficiency and quality of verification. In this paper, we present a series of research works, including what kinds of simulation techniques should be used and which methodology should be addressed. By using the Universal Verification Methodology (UVM) template, the verification modeling is done by us, and verification code is generated with FPGA automatic simulation tool (SunwiseFAS). the performance of this tool on automatic constructing simulation environment is presented, too. © 2020 IEEE.

关键词： field programmable gate arrays (FPGA)

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ZytleBot: FPGA integrated development platform for ROS based autonomous mobile robot 29

ZytleBot: FPGA integrated development platform for ROS based...

引用

29th international conference on field-programmable logic and applications (FPL)

作者： Nitta, Yasuhiro Tamura, So Takase, Hideki Kyoto Univ Grad Sch Informat Kyoto Japan

ISBN: (纸本)9781728148847

ZytleBot is an autonomous driving robot with an FPGA-integrated development platform that uses the Xilinx programmable system-on-chip (SoC). ZytleBot can run a course, turn right/left at intersections, avoid obstacles, detect traffic signals, and stop. All judgments and calculations necessary for driving are performed on the embedded system mounted on the robot. In ZytleBot, the main autonomous driving system uses the Robot Operating System (ROS) running on a CPU, and high-load processing is offloaded to the FPGA to enable real-time operation. the FPGA preprocesses road surface images acquired from the camera and detects traffic signals. We demonstrate the running of ZytleBot on a miniature course to win the FPT' 18 FPGA design competition(1). We also provide ZytleBot as a platform for the efficient development of FPGA-integrated ROS robots.

关键词： field programmable gate arrays Cameras Robot vision systems Hardware Software Mobile robots

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